Patents by Inventor Saurabh K. Tiwary

Saurabh K. Tiwary has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8782583
    Abstract: A system and method are disclosed for waveform based variational static timing analysis. A circuit is divided into its linear circuit parts and non-linear circuit parts and modeled together, by a combination of linear modeling techniques, into linear equations that may be represented by matrices. The linear equations in matrix form may be readily solved by a computer such that an input waveform to an input pin of the circuit can be sequentially “pushed” through the various interconnects and logic networks of the circuit to an output pin. Output voltage waveforms are obtained at each stage of the waveform pushing and may be used to perform static timing analysis.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: July 15, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Saurabh K Tiwary, Joel R. Phillips, Igor Keller
  • Patent number: 8375343
    Abstract: A system and method are disclosed for waveform based variational static timing analysis. A circuit is divided into its linear circuit parts and non-linear circuit parts and modeled together, by a combination of linear modeling techniques, into linear equations that may be represented by matrices. The linear equations in matrix form may be readily solved by a computer such that an input waveform to an input pin of the circuit can be sequentially “pushed” through the various interconnects and logic networks of the circuit to an output pin. Output voltage waveforms are obtained at each stage of the waveform pushing and may be used to perform static timing analysis.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: February 12, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Saurabh K. Tiwary, Joel R. Phillips, Igor Keller
  • Patent number: 8341567
    Abstract: A method is provided to formally verify a property of a circuit design comprising: receiving a description of at least a portion of the circuit; receiving an indication of search accuracy criteria; receiving a description of a relationship between current and voltage (I-V relationship) for one or more of devices of the circuit; converting each I-V relationship to a conservative approximation of such I-V relationship; assigning voltage labels to one or more terminals of one or more identified devices that indicate voltage relationships among the one or more terminals consistent with KVL; defining a respective current relationship among one or more respective sets of currents of the one or more of the identified devices that is consistent with KCL; searching for one or more combinations of current and voltage values that are within at least one region of each conservative approximation and that are consistent with the voltage labels and that are consistent with each respective defined current relationship; conv
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: December 25, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Saurabh K. Tiwary, Anubhav Gupta, Joel R. Phillips, Claudio Pinello, Radu Zlatanovici
  • Patent number: 8341572
    Abstract: A system and method are disclosed for waveform based variational static timing analysis. A circuit is divided into its linear circuit parts and non-linear circuit parts and modeled together, by a combination of linear modeling techniques, into linear equations that may be represented by matrices. The linear equations in matrix form may be readily solved by a computer such that an input waveform to an input pin of the circuit can be sequentially “pushed” through the various interconnects and logic networks of the circuit to an output pin. Output voltage waveforms are obtained at each stage of the waveform pushing and may be used to perform static timing analysis.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: December 25, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Saurabh K. Tiwary, Joel R. Phillips, Igor Keller
  • Patent number: 8245165
    Abstract: A system and method are disclosed for waveform based variational static timing analysis. A circuit is divided into its linear circuit parts and non-linear circuit parts and modeled together, by a combination of linear modeling techniques, into linear equations that may be represented by matrices. The linear equations in matrix form may be readily solved by a computer such that an input waveform to an input pin of the circuit can be sequentially “pushed” through the various interconnects and logic networks of the circuit to an output pin. Output voltage waveforms are obtained at each stage of the waveform pushing and may be used to perform static timing analysis.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: August 14, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Saurabh K. Tiwary, Joel R. Phillips, Igor Keller