Patents by Inventor Saurabh Khandelwal

Saurabh Khandelwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240105802
    Abstract: Integrated circuit structures having gate cut plugs removed from trench contacts, and methods of fabricating integrated circuit structures having gate cut plugs removed from trench contacts, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A gate cut plug extends through the gate electrode and the dielectric sidewall spacer. The gate cut plug extends into but not entirely through the conductive trench contact.
    Type: Application
    Filed: September 26, 2022
    Publication date: March 28, 2024
    Inventors: Leonard P. GULER, Marie CONTE, Charles H. WALLACE, Robert JOACHIM, Shengsi LIU, Saurabh ACHARYA, Nidhi KHANDELWAL, Kyle T. HORAK, Robert ROBINSON, Brandon PETERS
  • Publication number: 20240105716
    Abstract: Integrated circuit structures having uniform grid metal gate and trench contact cut, and methods of fabricating integrated circuit structures having uniform grid metal gate and trench contact cut, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A first dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. A second dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure laterally spaced apart from and parallel with the first dielectric cut plug structure.
    Type: Application
    Filed: September 27, 2022
    Publication date: March 28, 2024
    Inventors: Leonard P. GULER, Sukru YEMENICIOGLU, Mohit K. HARAN, Stephen M. CEA, Charles H. WALLACE, Tahir GHANI, Shengsi LIU, Saurabh ACHARYA, Thomas O'BRIEN, Nidhi KHANDELWAL, Marie T. CONTE, Prabhjot LUTHRA
  • Publication number: 20240053288
    Abstract: A sensor comprises a group of four memristors arranged in an array. Two of the memristors are connected in series as a first pair, and the other two memristors are connected in series as a second pair. The first and second pairs are connected in parallel between two connection points. Each memristor acts as a sensor element because it has an electrical resistance characteristic that is related to exposure to a species to be sensed. In the sensor, the resistance characteristic of the array between the first and second connection points is related to exposure to the species to be sensed. A sensor comprising a larger array can be composed of multiple groups of four memristors.
    Type: Application
    Filed: October 2, 2020
    Publication date: February 15, 2024
    Inventors: Abusaleh Jabir, Saurabh Khandelwal, Xiaohan Yang
  • Patent number: 11646749
    Abstract: A memristor-based circuit includes a voltage generator that applies a series of voltage pulses to a memristor to progressively change the resistance of the memristor. A comparator: receives an input electrical value; receives an electrical value based on the resistance of the memristor; compares the received values; and, based on the comparison, enables the application of the voltage pulses to the memristor by the voltage generator until a defined condition is satisfied. This circuit can be used to enable the memristor to be programmed to a desired resistance value, such as for use as a non-volatile memory. It can also enable the resistance of one memristor to be replicated to another memristor. By counting the number of applied voltage pulses, the circuit can be used as an encoder or analog-to-digital converter. Other variants of the circuit enable construction of a decoder or digital-to-analog converter, and an authentication circuit.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: May 9, 2023
    Assignee: OXFORD BROOKES UNIVERSITY
    Inventors: Abusaleh Jabir, Saurabh Khandelwal, Xiaohan Yang
  • Publication number: 20220329254
    Abstract: A memristor-based circuit includes a voltage generator that applies a series of voltage pulses to a memristor to progressively change the resistance of the memristor. A comparator: receives an input electrical value; receives an electrical value based on the resistance of the memristor; compares the received values; and, based on the comparison, enables the application of the voltage pulses to the memristor by the voltage generator until a defined condition is satisfied. This circuit can be used to enable the memristor to be programmed to a desired resistance value, such as for use as a non-volatile memory. It can also enable the resistance of one memristor to be replicated to another memristor. By counting the number of applied voltage pulses, the circuit can be used as an encoder or analog-to-digital converter. Other variants of the circuit enable construction of a decoder or digital-to-analog converter, and an authentication circuit.
    Type: Application
    Filed: April 15, 2020
    Publication date: October 13, 2022
    Inventors: Abusaleh Jabir, Saurabh Khandelwal, Xiaohan Yang