Patents by Inventor Saurabh Lodha

Saurabh Lodha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11983278
    Abstract: This disclosure relates generally to data anonymization using clustering techniques. In Typically, data anonymization using global recoding can overgeneralize the data. However, preservation of information while anonymization the data is of equal importance as obscuring the relevant information that can be used by the attackers. The disclosed method and system utilized attribute taxonomy tree for generalization to optimize the generalization of the records. The disclosed method uses clustering-based approach and after clustering, each cluster is solved independently using ILP model for K-Anonymization. The ILP model is solved by generalizing the value of the attributes. Sometimes, even after clustering the number of possible patterns is large, thus the disclosed method generates patterns on the fly during multiple iterations.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: May 14, 2024
    Assignee: Tata Consultancy Services Limited
    Inventors: Saket Saurabh, Arun Ramamurthy, Sutapa Mondal, Mangesh Sharad Gharote, Sachin Premsukh Lodha
  • Publication number: 20230004478
    Abstract: Systems and methods are provided for performing, at a server, a stack trace of an application at a predetermined interval to generate a plurality of stack traces, where each stack trace of the plurality of stack traces is from a different point in time based on the predetermined interval. The stack trace is performed when the application is operating normally and when the application has had a failure. The plurality of stack traces stored are indexed by timestamp. The server may determine a state of the application based on at least one of the plurality of stack traces. The server may condense data for at least one of the plurality of stack traces that are indexed using predetermined failure scenarios for the application. The server may generate a report based on the condensed data and the state of the application, and may transmit the report for display.
    Type: Application
    Filed: July 2, 2021
    Publication date: January 5, 2023
    Inventors: Ben Susman, Christian Bayer, Sergei Babovich, Sanyogita Sudhir Ranade, Saurabh Lodha, Timothy Cassidy, Krishnamurthy Muralidhar, Derek Forrest, Bing Xia, Kevin Fairfax
  • Publication number: 20180226278
    Abstract: Systems and methods of etching a semiconductor substrate may include flowing an oxygen-containing precursor into a substrate processing region of a semiconductor processing chamber. The substrate processing region may house the semiconductor substrate, and the semiconductor substrate may include an exposed metal-containing material. The methods may include flowing a nitrogen-containing precursor into the substrate processing region. The methods may further include removing an amount of the metal-containing material.
    Type: Application
    Filed: February 6, 2017
    Publication date: August 9, 2018
    Applicant: Applied Materials, Inc.
    Inventors: Ranga Rao Arnepalli, Prerna Sonthalia Goradia, Robert Jan Visser, Nitin Ingle, Mikhail Korolik, Jayeeta Biswas, Saurabh Lodha
  • Patent number: 10043684
    Abstract: Systems and methods of etching a semiconductor substrate may include flowing an oxygen-containing precursor into a substrate processing region of a semiconductor processing chamber. The substrate processing region may house the semiconductor substrate, and the semiconductor substrate may include an exposed metal-containing material. The methods may include flowing a nitrogen-containing precursor into the substrate processing region. The methods may further include removing an amount of the metal-containing material.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: August 7, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Ranga Rao Arnepalli, Prerna Sonthalia Goradia, Robert Jan Visser, Nitin Ingle, Mikhail Korolik, Jayeeta Biswas, Saurabh Lodha
  • Patent number: 7861406
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include amorphizing at least one contact area of a source/drain region of a transistor structure by implanting through at least one contact opening, forming a first layer of metal on the at least one contact area, forming a second layer of metal on the first layer of metal, selectively etching a portion of the second metal layer, annealing the at least one contact area to form at least one silicide, and removing the unreacted first metal layer and second metal layer from the transistor structure and forming a conductive material in the at least one contact opening.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: January 4, 2011
    Assignee: Intel Corporation
    Inventors: Saurabh Lodha, Pushkar Ranade, Christopher Auth
  • Publication number: 20080237603
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include amorphizing at least one contact area of a source/drain region of a transistor structure by implanting through at least one contact opening, forming a first layer of metal on the at least one contact area, forming a second layer of metal on the first layer of metal, selectively etching a portion of the second metal layer, and annealing the at least one contact area to form at least one silicide.
    Type: Application
    Filed: March 29, 2007
    Publication date: October 2, 2008
    Inventors: Saurabh Lodha, Pushkar Ranade, Christopher Auth