Patents by Inventor Saurabh Mishra

Saurabh Mishra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9646268
    Abstract: The systems and methods of the present application include a parts planning application (PPA) configured such that a bill of material (BOM) structure is automatically managed from a product data management (PDM) application, while supporting multiple product assemblies within a same project space and operating from a common code base. The PPA of the present application includes cross-functional attribute participation and is editable by all users simultaneously worldwide, thus eliminating the need for a dedicated project data administrator. The PPA of the present application enables daily or weekly management reviews, and attributes security managed by the functional group. The PPA of the present application fosters reduced data entry due to automated population of design structure and attributes from an existing PDM application and/or an enterprise resource planning (ERP) application.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: May 9, 2017
    Assignee: Brunswick Corporation
    Inventors: Nat Workman, Carl Wendtland, Saurabh Mishra
  • Publication number: 20160261433
    Abstract: A receiver circuit for estimating a state of an uplink channel between a wireless communication unit and a base station in a wireless communication system computes a conditioned Channel Impulse Response (CIR), the amount of conditioning being based on the noise present in the channel. A CIR and a Noise Variance are estimated from a Sounding Reference Signal received from the wireless communication unit. The estimated CIR is conditioned by comparing it with an adaptive threshold value selected from a look up table that lists threshold values against Noise Variance values. The threshold value further conditions the CIR to eliminate noise and interference. The conditioned CIR is converted into the frequency domain and used to provide a channel gain estimate which, together with noise estimates, is used to determine a Signal to Interference Noise Ratio (SINR) for the channel.
    Type: Application
    Filed: March 2, 2015
    Publication date: September 8, 2016
    Inventors: SAURABH MISHRA, Ankush Jain
  • Publication number: 20160119887
    Abstract: A base station and method of synchronizing with a user equipment (UE) in a cell of the base station. The base station signals to the UE an indication relating to a subset of preambles chosen for synchronization with the cell from a set of preambles derivable from one or more given root sequences. The subset of preambles is chosen to provide an increased cell radius compared to the cell radius achievable if the specified full set of preambles for random access procedures was generated from the given root sequences using a given cyclic shift value.
    Type: Application
    Filed: October 27, 2014
    Publication date: April 28, 2016
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Gopikrishna Charipadi, Ankush Jain, Maneesh Gupta, Saurabh Mishra
  • Publication number: 20150286044
    Abstract: The invention relates to an image processing method and system for constructing composite image with extended depth of field. The composite image may be constructed from a plurality of source images of a scene stored in an image stack. The method includes aligning the images in the image stack such that every image in the image stack is aligned with other images in the stack, performing illumination and color correction on the aligned images in the image stack, generating an energy matrix for each pixel of each illumination and color corrected image in the image stack by computing energy content for each pixel, generating a raw index map that contains the location of every pixels having maximum energy level among all the images in the image stack, generating degree of defocus ma and constructing the composite image.
    Type: Application
    Filed: November 4, 2013
    Publication date: October 8, 2015
    Applicant: L&T Technology Services Limited
    Inventors: Rabi Rout, Vajendra Desai, Harikrishnan Ramaraju, Gineesh Sukumaran, Sistu Ganesh, Devvrata Priyadarshi, Eldho Abraham, Saurabh Mishra, Sudipta Kumar Sahoo, Nivedita Tripathi, Siddhartha Goutham, Kunal Gauraw
  • Patent number: 8832171
    Abstract: In one embodiment, a processor performs a method of generating pipelined data read indexes and data write indexes for a Prime Factor Algorithm (PFA) Discrete Fourier Transform (DFT) without look-up tables. The processor is adapted to factorize an ā€˜N’ point PFA DFT into one or more mutually prime factors and zero or more non-prime factors, calculate a 0th column index for an ith row (Xi0), calculate an IndCor when the value of Xi0 equals zero and when a row number (i) does not equal zero, calculate Xij, generate the data read indexes, perform a DFT kernel computation on Lk point for the mutually prime factors and the non-prime factors, and generate the data write indexes for the mutually prime factors and the non-prime factors. Xij represents ith row and jth column of 2D input Buffer and enables a selection of a linear index from the 2D input buffer.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: September 9, 2014
    Assignee: Saankhya Labs Pvt. Ltd.
    Inventors: Gururaj Padaki, Saurabh Mishra, Suman Sanisetty
  • Patent number: 8812569
    Abstract: A method for implementing a digital filter is provided. The method includes (a) determining a bit-width of an incoming data sample of an incoming signal by measuring a distance between a leading zero or one of the incoming data sample and a trailing zero of the incoming data sample. The incoming data sample is obtained by sampling the incoming signal at a pre-defined time interval, (b) obtaining bit-width multipliers with variable bit-widths based on a first probability distribution function (PDF) of bit-widths of incoming data samples, (c) allocating the incoming data sample and a filter coefficient based on the bit-width of the incoming data sample and a bit-width of the filter coefficient to one bit-width multiplier of the bit-width multipliers, and (d) performing a multiply operation of a Multiply and Accumulate (MAC) operation on the one bit-width multiplier to generate an output of the digital filter.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: August 19, 2014
    Assignee: Saankhya Labs Private Limited
    Inventors: Parag Naik, Anindya Saha, Gururaj Padaki, Subrahmanya Kondageri Shankaraiah, Saurabh Mishra
  • Patent number: 8644429
    Abstract: A wide band receiver to select and demodulate an input signal with single scan spectrum sensing by performing filtering on the input signal in digital domain to achieve improved selectivity and sensitivity is provided. The input signal includes one or more narrowband radio frequency (RF) signals. The wide band receiver includes a wide band tuner that down converts the one or more narrowband RF signals to one or more IF signals. An analog to digital converter (ADC) converts the one or more IF signals to one or more digital signals. A filter rejects out-of-band signals from the one or more digital signals to achieve the improved selectivity. A numeric controlled oscillator (NCO) selects at least one narrowband digital signal from the digital signals based on a phase value obtained from a spectrum selection control unit. A demodulator demodulates the narrowband digital signal to obtain a demodulated digital signal.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: February 4, 2014
    Assignee: Saankhya Labs Private Limited
    Inventors: Subramanian Harish Krishnan, Saurabh Mishra, Parag Naik, Subrahmanya Kondageri Shankaraiah, Gururaj Padki, Santosh Billava
  • Patent number: 8611471
    Abstract: A system and method for reducing implementation complexity for estimation of a Carrier Frequency Offset (CFO) and a Symbol Timing Offset (STO) for an input signal for spectrally shaped multiple communication standards. The system is implemented by replacing multiplier with shifters. The system includes a CFO estimation block, a STO estimation block, and a band extraction block that extracts a lower band edge and an upper band edge of the input signal. The STO estimation block includes (i) a sample error generation block that computes a sampling timing error value, and (ii) a Phase Lock Loop block that estimates a frequency error and a phase error corresponding to the sampling timing error value. The CFO estimation block includes (i) a carrier offset error generation block that generates a carrier offset error value, and (ii) a leaky average block for performing a filter operation.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: December 17, 2013
    Assignee: Saankhya Labs Pvt. Ltd.
    Inventors: Saurabh Mishra, Parag Naik, Subrahmanya Kondageri Shankaraiah, S Harish Krishnan, Gururaj Padaki
  • Patent number: 8611472
    Abstract: A receiver for reducing acquisition time of a Carrier Frequency Offset (CFO) of an input intermediate frequency (IF) signal with M-PSK modulated preamble using spectral based analysis is provided. The receiver includes an analog to digital converter that converts the input IF signal into a digital signal, a down conversion unit that down converts the digital signal to a baseband complex signal, and a CFO estimation block that estimates the CFO. The CFO estimation block includes a carrier harmonic generation unit that generates an output of carrier Mth harmonic without modulation in the baseband complex signal, a spectral mapping unit that spectrally maps the carrier harmonic using complex Fast Fourier Transform, a spectral analysis unit that performs peak search on the spectrally mapped carrier Mth harmonic to obtain a peak position (PPOS), and a carrier frequency offset estimation unit that receives the peak position (PPOS) and estimates the CFO.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: December 17, 2013
    Assignee: Saankhya Labs Private Limited
    Inventors: Saurabh Mishra, Subrahmanya Kondageri Shankaraiah, Subramanian Harish Krishnan
  • Publication number: 20120284318
    Abstract: A method for implementing a digital filter is provided. The method includes (a) determining a bit-width of an incoming data sample of an incoming signal by measuring a distance between a leading zero or one of the incoming data sample and a trailing zero of the incoming data sample. The incoming data sample is obtained by sampling the incoming signal at a pre-defined time interval, (b) obtaining bit-width multipliers with variable bit-widths based on a first probability distribution function (PDF) of bit-widths of incoming data samples, (c) allocating the incoming data sample and a filter coefficient based on the bit-width of the incoming data sample and a bit-width of the filter coefficient to one bit-width multiplier of the bit-width multipliers, and (d) performing a multiply operation of a Multiply and Accumulate (MAC) operation on the one bit-width multiplier to generate an output of the digital filter.
    Type: Application
    Filed: May 2, 2012
    Publication date: November 8, 2012
    Applicant: SAANKHYA LABS PRIVATE LIMITED
    Inventors: Parag NAIK, Anindya SAHA, Gururaj PADAKI, Subrahmanya Kondageri SHANKARAIAH, Saurabh MISHRA
  • Publication number: 20120269297
    Abstract: A receiver for reducing acquisition time of a Carrier Frequency Offset (CFO) of an input intermediate frequency (IF) signal with M-PSK modulated preamble using spectral based analysis is provided. The receiver includes an analog to digital converter that converts the input IF signal into a digital signal, a down conversion unit that down converts the digital signal to a baseband complex signal, and a CFO estimation block that estimates the CFO. The CFO estimation block includes a carrier harmonic generation unit that generates an output of carrier Mth harmonic without modulation in the baseband complex signal, a spectral mapping unit that spectrally maps the carrier harmonic using complex Fast Fourier Transform, a spectral analysis unit that performs peak search on the spectrally mapped carrier Mth harmonic to obtain a peak position (PPOS), and a carrier frequency offset estimation unit that receives the peak position (PPOS) and estimates the CFO.
    Type: Application
    Filed: April 13, 2012
    Publication date: October 25, 2012
    Applicant: Saankhya Labs Private Limited
    Inventors: Saurabh Mishra, Subrahmanya Kondageri Shankaraiah, Subramanian Harish Krishnan
  • Publication number: 20120269300
    Abstract: A wide band receiver to select and demodulate an input signal with single scan spectrum sensing by performing filtering on the input signal in digital domain to achieve improved selectivity and sensitivity is provided. The input signal includes one or more narrowband radio frequency (RF) signals. The wide band receiver includes a wide band tuner that down converts the one or more narrowband RF signals to one or more IF signals. An analog to digital converter (ADC) converts the one or more IF signals to one or more digital signals. A filter rejects out-of-band signals from the one or more digital signals to achieve the improved selectivity. A numeric controlled oscillator (NCO) selects at least one narrowband digital signal from the digital signals based on a phase value obtained from a spectrum selection control unit. A demodulator demodulates the narrowband digital signal to obtain a demodulated digital signal.
    Type: Application
    Filed: April 13, 2012
    Publication date: October 25, 2012
    Applicant: Saankhya Labs Private Limited
    Inventors: Subramanian Harish Krishnan, Saurabh Mishra, Parag Naik, Subrahmanya Kondageri Shankaraiah, Gururaj Padaki, Santosh Billava
  • Publication number: 20120250750
    Abstract: A system and method for reducing implementation complexity for estimation of a Carrier Frequency Offset (CFO) and a Symbol Timing Offset (STO) for an input signal for spectrally shaped multiple communication standards. The system is implemented by replacing multiplier with shifters. The system includes a CFO estimation block, a STO estimation block, and a band extraction block that extracts a lower band edge and an upper band edge of the input signal. The STO estimation block includes (i) a sample error generation block that computes a sampling timing error value, and (ii) a Phase Lock Loop block that estimates a frequency error and a phase error corresponding to the sampling timing error value. The CFO estimation block includes (i) a carrier offset error generation block that generates a carrier offset error value, and (ii) a leaky average block for performing a filter operation.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 4, 2012
    Applicant: SAANKHYA LABS PVT. LTD.
    Inventors: Saurabh Mishra, Parag Naik, Subrahmanya Kondageri Shankaraiah, S. Harish Krishnan, Gururaj Padaki
  • Publication number: 20120254274
    Abstract: In one embodiment, a processor performs a method of generating pipelined data read indexes and data write indexes for a Prime Factor Algorithm (PFA) Discrete Fourier Transform (DFT) without look-up tables. The processor is adapted to factorize an ā€˜N’ point PFA DFT into one or more mutually prime factors and zero or more non-prime factors, calculate a 0th column index for an ith row (Xi0), calculate an IndCor when the value of Xi0 equals zero and when a row number (i) does not equal zero, calculate Xij, generate the data read indexes, perform a DFT kernel computation on Lk point for the mutually prime factors and the non-prime factors, and generate the data write indexes for the mutually prime factors and the non-prime factors. Xij represents ith row and jth column of 2D input Buffer and enables a selection of a linear index from the 2D input buffer.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 4, 2012
    Applicant: SAANKHYA LABS PVT. LTD.
    Inventors: Gururaj Padaki, Saurabh Mishra, Suman Sanisetty