Patents by Inventor Saurabh Mookerjea

Saurabh Mookerjea has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • TFET based 6T SRAM cell
    Patent number: 8369134
    Abstract: Memory devices and methods of operation are provided. A memory device includes first and second cross-coupled inverters and first and second access transistors coupled to an input node of the second inverter. The memory device also includes a control circuit for providing a first reference voltage at a first ground node of the first inverter and a second reference voltage at a second ground node of the second inverter. The first access transistor is configured to conduct current from a first bit line to the input node and to provide substantially no current conduction from the input node to the first bit line. The second access transistor is configured to conduct current from the input node to one of the first bit line and a second bit line and to provide substantially no current conduction from the input node to the one of first and second bit lines.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: February 5, 2013
    Assignee: The Penn State Research Foundation
    Inventors: Jawar Singh, Ramakrishnan Krishnan, Saurabh Mookerjea, Suman Datta, Vijaykrishnan Narayanan
  • TFET BASED 6T SRAM CELL
    Publication number: 20120106236
    Abstract: Memory devices and methods of operation are provided. A memory device includes first and second cross-coupled inverters and first and second access transistors coupled to an input node of the second inverter. The memory device also includes a control circuit for providing a first reference voltage at a first ground node of the first inverter and a second reference voltage at a second ground node of the second inverter. The first access transistor is configured to conduct current from a first bit line to the input node and to provide substantially no current conduction from the input node to the first bit line. The second access transistor is configured to conduct current from the input node to one of the first bit line and a second bit line and to provide substantially no current conduction from the input node to the one of first and second bit lines.
    Type: Application
    Filed: October 27, 2010
    Publication date: May 3, 2012
    Applicant: THE PENN STATE RESEARCH FOUNDATION
    Inventors: Jawar Singh, Ramakrishnan Krishnan, Saurabh Mookerjea, Suman Datta, Vijaykrishnan Narayanan