Patents by Inventor Saurabh MORARKA
Saurabh MORARKA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961836Abstract: An integrated circuit structure comprises one or more fins extending above a surface of a substrate over an N-type well. A gate is over and in contact with the one or more fins. A second shallow N-type doping is below the gate and above the N-type well.Type: GrantFiled: September 28, 2018Date of Patent: April 16, 2024Assignee: Intel CorporationInventors: Hyung-Jin Lee, Mark Armstrong, Saurabh Morarka, Carlos Nieva-Lozano, Ayan Kar
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Patent number: 11869987Abstract: Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.Type: GrantFiled: July 7, 2022Date of Patent: January 9, 2024Assignee: Intel CorporationInventors: Ayan Kar, Saurabh Morarka, Carlos Nieva-Lozano, Kalyan Kolluru, Biswajeet Guha, Chung-Hsun Lin, Brian Greene, Tahir Ghani
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Publication number: 20230420578Abstract: A varactor device includes a support structure, an electrically conductive layer at the backside of the support structure, two semiconductor structures including doped semiconductor materials, two contact structures, and a semiconductor region. Each contract structure is electrically conductive and is connected to a different one of the semiconductor structures A contract structure couples the corresponding semiconductor structure to the electrically conductive layer. The semiconductor region is between the two semiconductor structures and can be connected to the two semiconductor structures. The semiconductor region may include non-planar semiconductor structures coupled with a gate. The gate may be coupled to another electrically conductive layer at the frontside of the support structure. The varactor device may further include a pair of additional semiconductor regions that are electrically insulated from each other.Type: ApplicationFiled: June 24, 2022Publication date: December 28, 2023Applicant: Intel CorporationInventors: Ayan Kar, Kalyan C. Kolluru, Nicholas A. Thomson, Vijaya Bhaskara Neeli, Said Rami, Saurabh Morarka, Karthik Krishaswamy, Mauro J. Kobrinsky
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Publication number: 20230299135Abstract: Techniques are provided herein to form an integrated circuit having any number of partial gate cut structures between adjacent semiconductor devices. Neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate structure extending over the semiconductor regions of the neighboring semiconductor devices. In some such examples, a partial gate cut structure is present between a given pair of neighboring semiconductor devices. The partial gate cut structure acts as a dielectric pillar between the semiconductor structures that allows the conductive gate layer (from the gate structure) to extend above and/or below it such that the gates of each of the semiconductor devices remain electrically coupled together. The gate cut structure itself removes a portion of the gate layer from between the semiconductor devices, thus reducing parasitic capacitance.Type: ApplicationFiled: March 17, 2022Publication date: September 21, 2023Applicant: Intel CorporationInventors: Leonard P. Guler, Tahir Ghani, Saurabh Morarka, Charles H. Wallace
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Publication number: 20230275124Abstract: Techniques are provided herein to form semiconductor devices having epitaxial diffusion regions (e.g., source and/or drain regions) wrapped by a conductive contact. In an example, a semiconductor device includes a source or drain region and a conductive layer that extends around the source or drain region such that the conductive layer at least contacts the sidewalls of the source or drain region or wraps completely around the source or drain region. In some examples, a conducive contact extends upward through a thickness of an adjacent dielectric layer and contacts the conductive layer from below, thus forming a backside contact. By forming a conductive layer around multiple sides of the source or drain region (rather than just contacting a top or bottom surface) more surface area of the source or drain region is contacted thus providing an improved ohmic contact and a lower overall contact resistance.Type: ApplicationFiled: February 25, 2022Publication date: August 31, 2023Applicant: Intel CorporationInventors: Leonard P. Guler, Gilbert Dewey, Saurabh Morarka, Sikandar Abbas, Mohammad Hasan
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Publication number: 20230197848Abstract: Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.Type: ApplicationFiled: February 21, 2023Publication date: June 22, 2023Inventors: Michael Jackson, Anand Murthy, Glenn Glass, Saurabh Morarka, Chandra Mohapatra
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Patent number: 11610995Abstract: Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.Type: GrantFiled: September 9, 2022Date of Patent: March 21, 2023Assignee: Daedalus Prime LLCInventors: Michael Jackson, Anand Murthy, Glenn Glass, Saurabh Morarka, Chandra Mohapatra
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Publication number: 20230006063Abstract: Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.Type: ApplicationFiled: September 9, 2022Publication date: January 5, 2023Inventors: Michael Jackson, Anand Murthy, Glenn Glass, Saurabh Morarka, Chandra Mohapatra
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Publication number: 20220399373Abstract: An integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. A first dielectric gate spacer is laterally around the first gate stack and has a portion along an end of the first gate stack and in the gap. A second dielectric gate spacer is laterally around the second gate stack and has a portion along an end of the second gate stack and in the gap. The portion of the second dielectric gate spacer is laterally merged with the portion of the first dielectric gate spacer in the gap.Type: ApplicationFiled: June 15, 2021Publication date: December 15, 2022Inventors: Leonard P. GULER, Chanaka MUNASINGHE, Makram ABD EL QADER, Marie CONTE, Saurabh MORARKA, Elliot N. TAN, Krishna GANESAN, Mohit K. HARAN, Charles H. WALLACE, Tahir GHANI, Sean PURSEL
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Publication number: 20220399445Abstract: Conductive via bars self-aligned to gate ends are described. In an example, an integrated circuit structure includes a plurality of gate structures. The integrated circuit structure also includes a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers laterally surrounding a corresponding one of the plurality of gate structures. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. A conductive via bar is along ends of the plurality of gate structures and ends of the plurality of conductive trench contact structures, wherein the plurality of dielectric spacers is between the ends of the plurality of gate structures and the conductive via bar.Type: ApplicationFiled: June 14, 2021Publication date: December 15, 2022Inventors: Leonard P. GULER, Tahir GHANI, Charles H. WALLACE, Conor P. PULS, Walid M. HAFEZ, Sairam SUBRAMANIAN, Justin S. SANDFORD, Saurabh MORARKA, Sean PURSEL, Mohammad HASAN
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Patent number: 11515424Abstract: Disclosed herein are field-effect transistors with asymmetric gate stacks. An example transistor includes a channel material and an asymmetric gate stack, provided over a portion of the channel material between source and drain (S/D) regions. The gate stack is asymmetric in that a thickness of a gate dielectric of a portion of the gate stack closer to one of the S/D regions is different from that of a portion of the gate stack closer to the other S/D region, and in that a work function (WF) material of a portion of the gate stack closer to one of the S/D regions is different from a WF material of a portion of the gate stack closer to the other S/D region. Transistors as described herein exploit asymmetry in the gate stacks to improve the transistor performance in terms of high breakdown voltage, high gain, and/or high output resistance.Type: GrantFiled: February 8, 2019Date of Patent: November 29, 2022Assignee: Intel CorporationInventors: Said Rami, Hyung-Jin Lee, Saurabh Morarka, Guannan Liu, Qiang Yu, Bernhard Sell, Mark Armstrong
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Publication number: 20220344519Abstract: Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.Type: ApplicationFiled: July 7, 2022Publication date: October 27, 2022Inventors: Ayan KAR, Saurabh MORARKA, Carlos NIEVA-LOZANO, Kalyan KOLLURU, Biswajeet GUHA, Chung-Hsun LIN, Brian GREENE, Tahir GHANI
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Patent number: 11482618Abstract: Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.Type: GrantFiled: April 19, 2022Date of Patent: October 25, 2022Assignee: Daedalus Prime LLCInventors: Michael Jackson, Anand Murthy, Glenn Glass, Saurabh Morarka, Chandra Mohapatra
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Patent number: 11417781Abstract: Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.Type: GrantFiled: March 25, 2020Date of Patent: August 16, 2022Assignee: Intel CorporationInventors: Ayan Kar, Saurabh Morarka, Carlos Nieva-Lozano, Kalyan Kolluru, Biswajeet Guha, Chung-Hsun Lin, Brian Greene, Tahir Ghani
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Patent number: 11411110Abstract: Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.Type: GrantFiled: October 12, 2021Date of Patent: August 9, 2022Assignee: Intel CorporationInventors: Michael Jackson, Anand Murthy, Glenn Glass, Saurabh Morarka, Chandra Mohapatra
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Publication number: 20220238714Abstract: Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.Type: ApplicationFiled: April 19, 2022Publication date: July 28, 2022Inventors: Michael Jackson, Anand Murthy, Glenn Glass, Saurabh Morarka, Chandra Mohapatra
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Publication number: 20220059699Abstract: Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.Type: ApplicationFiled: October 12, 2021Publication date: February 24, 2022Inventors: Michael Jackson, Anand Murthy, Glenn Glass, Saurabh Morarka, Chandra Mohapatra
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Publication number: 20210305436Abstract: Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.Type: ApplicationFiled: March 25, 2020Publication date: September 30, 2021Inventors: Ayan KAR, Saurabh MORARKA, Carlos NIEVA-LOZANO, Kalyan KOLLURU, Biswajeet GUHA, Chung-Hsun LIN, Brian GREENE, Tahir GHANI
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Patent number: 11107920Abstract: Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.Type: GrantFiled: July 11, 2019Date of Patent: August 31, 2021Assignee: Intel CorporationInventors: Michael Jackson, Anand Murthy, Glenn Glass, Saurabh Morarka, Chandra Mohapatra
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Publication number: 20200259018Abstract: Disclosed herein are field-effect transistors with asymmetric gate stacks. An example transistor includes a channel material and an asymmetric gate stack, provided over a portion of the channel material between source and drain (S/D) regions. The gate stack is asymmetric in that a thickness of a gate dielectric of a portion of the gate stack closer to one of the S/D regions is different from that of a portion of the gate stack closer to the other S/D region, and in that a work function (WF) material of a portion of the gate stack closer to one of the S/D regions is different from a WF material of a portion of the gate stack closer to the other S/D region. Transistors as described herein exploit asymmetry in the gate stacks to improve the transistor performance in terms of high breakdown voltage, high gain, and/or high output resistance.Type: ApplicationFiled: February 8, 2019Publication date: August 13, 2020Applicant: Intel CorporationInventors: Said Rami, Hyung-Jin Lee, Saurabh Morarka, Guannan Liu, Qiang Yu, Bernhard Sell, Mark Armstrong