Abstract: Memory with asymmetric power delivery for keeper cells in the memory are provided. In some embodiments, first and second power delivery circuits use separate first and second independently regulated power supplies. The first supply may be a supply nominally used for the memory structure, while the second supply may be lower than the first supply. In some embodiments, during a write operation, the first (higher) supply is used for one of the logic elements in a keeper cell, while the second (lower) supply is used for the other keeper logic element.