Abstract: Various aspects of the disclosure are directed to circuitry coupled for controlling current flow, such as in a cascode arrangement. As may be consistent with one or more embodiments, an apparatus includes a first transistor having a gate, source, channel and drain, and a second transistor having a gate, and having a stacked source, channel and drain. A conductive clip plate electrically connects the drain of the second transistor to the source of the first transistor, and another conductor electrically connects the source of the second transistor to the gate of the first transistor. The second transistor operates with the connecting structure to provide power by controlling the first transistor in an off-state and in an on-state.

Abstract: A field effect transistor semiconductor device having a compact device footprint for use in automotive and hot swap applications. The device includes a plurality of field effect transistor cells with the plurality of transistor cells having at least one low threshold voltage transistor cell and at least one high threshold voltage transistor cell arranged on a substrate. The field effect transistor semiconductor device is configured and arranged to operate the at least one high threshold voltage transistor cell during linear mode operation, and operate both the low threshold voltage transistor cell and the high threshold voltage transistor cell during resistive mode operation. Further provided is a method of operating field effect transistor semiconductor device including a plurality of field effect transistor cells that includes at least one low threshold voltage transistor cell and at least one high threshold voltage transistor cell.

Abstract: A heterojunction semiconductor device is disclosed. The heterojunction semiconductor device includes a substrate and a multilayer structure disposed on the substrate. The multilayer structure includes a first layer comprising a first semiconductor disposed on top of the substrate, and a second layer comprising a second semiconductor disposed on top of the first layer to define an interface between the first layer and the second layer. The second semiconductor is different from the first semiconductor such that a Two-Dimensional Electron Gas forms adjacent to the interface. The device also includes a first terminal electrically coupled to a first area of the interface between the first layer and second layer and a second terminal electrically coupled to a second area of the interface between the first layer and second layer. The device also includes an electrically conducting channel comprising an implanted region at bottom and sidewalls.

Abstract: A field effect transistor semiconductor device having a compact device footprint for use in automotive and hot swap applications. The device includes a plurality of field effect transistor cells with the plurality of transistor cells having at least one low threshold voltage transistor cell and at least one high threshold voltage transistor cell arranged on a substrate. The field effect transistor semiconductor device is configured and arranged to operate the at least one high threshold voltage transistor cell during linear mode operation, and operate both the low threshold voltage transistor cell and the high threshold voltage transistor cell during resistive mode operation. Further provided is a method of operating field effect transistor semiconductor device including a plurality of field effect transistor cells that includes at least one low threshold voltage transistor cell and at least one high threshold voltage transistor cell.

Abstract: A unit test and automation framework (UTAF) system and method are disclosed for unit testing. A unit definition file that includes properties of the unit being tested may be compiled to generate a skeleton code that describes a structure of the unit and the interactions of the unit with other units. One or more interactions may be overridden to generate a unit production code for the unit. A unit testing (UT) engine may enable interactions between the unit and the other units to run test cases on the unit production code as part of unit testing. Various components of the UTAF system may provide commands to or perform functions for the UT engine to perform the unit testing, such as providing test commands, displaying statistics, providing interface messaging between the unit and the plurality of other units, provide commands for record and replay testing, and other information.

Abstract: Techniques for providing predictive metrics relating to employment positions are provided. A method may include receiving, by a computing device, data relating to a plurality of employment positions, wherein the data is received from a plurality of customers. The computing device may aggregate the data received from the plurality of customers and may determine statistics using the aggregated data, which are based on each of the plurality of employment positions. The computing device may generate one or more predictive metrics relating to the plurality of employment positions using one or more of the statistics.

Abstract: Various aspects of the disclosure are directed to circuitry coupled for controlling current flow, such as in a cascode arrangement. As may be consistent with one or more embodiments, an apparatus includes a first transistor having a gate, source, channel and drain, and a second transistor having a gate, and having a stacked source, channel and drain. A conductive clip plate electrically connects the drain of the second transistor to the source of the first transistor, and another conductor electrically connects the source of the second transistor to the gate of the first transistor. The second transistor operates with the connecting structure to provide power by controlling the first transistor in an off-state and in an on-state.

Abstract: Systems and methods for time slot allocation of time slots for bundled links in a shared mesh GMPLS for protect paths with different of COS may include time slot allocation divided into multiple phases with each phase having some qualification criterion to go to next phase or exit if the criterion is not met. For example, allocation of time slots for a circuit may include three phases—component selection phase, a connection admission phase, and an optimization phase.

Abstract: A heterojunction semiconductor device is disclosed. The heterojunction semiconductor device includes a substrate and a multilayer structure disposed on the substrate. The multilayer structure includes a first layer comprising a first semiconductor disposed on top of the substrate, and a second layer comprising a second semiconductor disposed on top of the first layer to define an interface between the first layer and the second layer. The second semiconductor is different from the first semiconductor such that a Two-Dimensional Electron Gas forms adjacent to the interface. The device also includes a first terminal electrically coupled to a first area of the interface between the first layer and second layer and a second terminal electrically coupled to a second area of the interface between the first layer and second layer. The device also includes an electrically conducting channel comprising an implanted region at bottom and sidewalls.

Abstract: Techniques for providing predictive metrics relating to employment positions are provided. A method may include receiving, by a computing device, data relating to a plurality of employment positions, wherein the data is received from a plurality of customers. The computing device may aggregate the data received from the plurality of customers and may determine statistics using the aggregated data, which are based on each of the plurality of employment positions. The computing device may generate one or more predictive metrics relating to the plurality of employment positions using one or more of the statistics.

Abstract: Techniques for providing predictive metrics relating to employment positions are provided. A method may include receiving, by a computing device, data relating to a plurality of employment positions, wherein the data is received from a plurality of customers. The computing device may aggregate the data received from the plurality of customers and may determine statistics using the aggregated data, which are based on each of the plurality of employment positions. The computing device may generate one or more predictive metrics relating to the plurality of employment positions using one or more of the statistics.

Abstract: Systems and methods for time slot allocation of time slots for bundled links in a shared mesh GMPLS for protect paths with different of COS may include time slot allocation divided into multiple phases with each phase having some qualification criterion to go to next phase or exit if the criterion is not met. For example, allocation of time slots for a circuit may include three phases—component selection phase, a connection admission phase, and an optimization phase.

Abstract: A method to dynamically resize an LSP without releasing it includes: establishing a first path through a network from a first device to a second device; receiving a request to resize the first path; establishing a second path identical to the first path; simultaneously transmitting communication signals on the first path and the second path; and switching all communication signals from the first path to the second path.

Abstract: Techniques for providing predictive metrics relating to employment positions are provided. A method may include receiving, by a computing device, data relating to a plurality of employment positions, wherein the data is received from a plurality of customers. The computing device may aggregate the data received from the plurality of customers and may determine statistics using the aggregated data, which are based on each of the plurality of employment positions. The computing device may generate one or more predictive metrics relating to the plurality of employment positions using one or more of the statistics.

Abstract: The present disclosure provides bandwidth defragmentation systems and methods in optical networks such as Optical Transport Network (OTN), Synchronous Optical Network (SONET), Synchronous Digital Hierarchy (SDH), Ethernet, and the like. In particular, the present invention includes bandwidth defragmentation algorithms that may be used within the context of a signaling and routing protocol to avoid bandwidth defragmentation. As such, the present invention defines a mechanism for computing an end to end path for a connection in a manner that avoids bandwidth fragmentation and provides for better network utilization. For example, the present invention may include a path computation based upon administrative weight and upon fragmentation costs. This may be implemented in existing signaling and routing protocols without changes to existing protocol messages used in topology discovery.

Abstract: The present disclosure provides bandwidth defragmentation systems and methods in optical networks such as Optical Transport Network (OTN), Synchronous Optical Network (SONET), Synchronous Digital Hierarchy (SDH), Ethernet, and the like. In particular, the present invention includes bandwidth defragmentation algorithms that may be used within the context of a signaling and routing protocol to avoid bandwidth defragmentation. As such, the present invention defines a mechanism for computing an end to end path for a connection in a manner that avoids bandwidth fragmentation and provides for better network utilization. For example, the present invention may include a path computation based upon administrative weight and upon fragmentation costs. This may be implemented in existing signaling and routing protocols without changes to existing protocol messages used in topology discovery.

Abstract: The present invention relates to salts of (R)-5-(2-phenylsulphonylethenyl)-3-(N-methylpyrrolidin-2-ylmethyl)-1H-indole of the formula: wherein HX is an acid selected from para-toluene sulfonic acid, benzene sulphonic acid, trifluoroacetic acid, methane sulphonic acid, formic acid and succinic acid; and to processes of preparing and using such salts.

Abstract: A system for controlling a power output is disclosed. The system includes a hydraulic actuator configured to output a first torque and a source of pressurized fluid configured to supply a flow of pressurized fluid to the hydraulic actuator. The system further includes a controller configured to control the flow of pressurized fluid as a function of the first torque, a predetermined torque, and changes to the first torque caused by a load operatively connected to the hydraulic actuator.

Abstract: A method is provided for controlling braking in a vehicle having a motor and a brake. The method includes sensing an actual operating parameter of the motor and receiving a desired operating parameter of the motor. The motor is controlled based on the actual operating parameter and the desired operating parameter of the motor. The brake is controlled based on the actual operating parameter and the desired operating parameter of the motor and an output from the motor control.

Abstract: A system is provided for controlling slip of a ground-engaging traction device of a work machine. The system includes an actual slip calculator operable to transmit an actual slip signal corresponding to an actual slip experienced by the work machine. The system also includes a ground condition selector operable to transmit a ground condition signal corresponding to a selected ground condition. A desired slip calculator is operable to transmit a desired slip signal based on the ground condition signal. A slip controller is coupled with the actual slip calculator and the desired slip calculator. The slip controller is operable to transmit a slip control signal based on the actual slip signal and the desired slip signal. The slip control signal controls the actual slip experienced by the work machine to achieve the desired slip.