Abstract: An error amplifier includes a first transistor having a first error amplifier input and having first and second current terminals, a second transistor having a second error amplifier input and having third and fourth current terminals, a first resistor coupled between a supply voltage terminal and the first current terminal, and a second resistor coupled between the supply voltage terminal and the third current termina. The error amplifier has a second stage circuit coupled to the first and second resistors. The second stage circuit has an error amplifier output. The second stage circuit is configured to cause less current to flow through the second stage circuit than a current that flows through either of the first or second resistors or the first or second transistors.

Abstract: Described embodiments include a circuit for dampening overshoot in a voltage regulator. The circuit includes a first and second offset voltage circuits, each having an input coupled to an input voltage terminal. A first comparator has a first comparator input coupled to the first offset output, and a second comparator input coupled to a reference voltage terminal. A second comparator has a third comparator input coupled to an output of the second offset circuit, and a fourth comparator input coupled to a voltage regulator output. An OR gate has first and second logic inputs and a logic output. The first and second logic inputs are coupled to the outputs of the first and second comparators, respectively. A turn-off circuit has a turn-off input coupled to the logic output, and is configured to provide a turn-off signal at a turn-off output to stop current flow from the voltage regulator output.

Abstract: Described embodiments include a circuit for reducing output voltage noise in a voltage regulator includes an amplifier having first and second amplifier inputs, a compensation terminal and an amplifier output. The first amplifier input is coupled to a reference voltage terminal, and the compensation terminal coupled to an output terminal. A buffer amplifier has a buffer input and a buffer output, and the buffer input is coupled to the amplifier output. A first transistor is coupled between a supply voltage terminal and the output terminal, and has a first control terminal that is coupled to the buffer output. A boost current injection circuit has a boost input and a boost output, and the boost input is coupled to the supply voltage terminal. A second transistor is coupled between the boost output and the compensation terminal, and has a second control terminal.

Abstract: Described embodiments include a circuit for dampening overshoot in a voltage regulator. The circuit includes a first and second offset voltage circuits, each having an input coupled to an input voltage terminal. A first comparator has a first comparator input coupled to the first offset output, and a second comparator input coupled to a reference voltage terminal. A second comparator has a third comparator input coupled to an output of the second offset circuit, and a fourth comparator input coupled to a voltage regulator output. An OR gate has first and second logic inputs and a logic output. The first and second logic inputs are coupled to the outputs of the first and second comparators, respectively. A turn-off circuit has a turn-off input coupled to the logic output, and is configured to provide a turn-off signal at a turn-off output to stop current flow from the voltage regulator output.

Abstract: An amplifier includes a first differential input pair of transistors having a first input terminal, a second input terminal, a first output terminal, and a second output terminal. A second differential input pair of transistors has a third input terminal, a fourth input terminal, a third output terminal, and a fourth output terminal. The first input terminal is coupled to the third input terminal, the second input terminal is coupled to the fourth input terminal, the first output terminal is coupled to the third output terminal, and the second output terminal is coupled to the fourth output terminal. A cross-over circuit has a control input coupled to the second fourth input terminals. The cross-over circuit is configured to vary an amount of bias current through the second differential input pair of transistors based on a magnitude of a voltage on the second and fourth input terminals.

Abstract: A circuit includes a first power transistor including a first control input and first and second current terminals. The circuit includes a second power transistor including a second control input and third and fourth current terminals. Third current terminal couples to the first current terminal, and the fourth current terminal couples to the second current terminal at an output node. An error amplifier generates an error signal based on a difference between a reference voltage and an output voltage on the output node. An adaptive buffer couples to an output of the error amplifier and couples to the first and second control inputs. The adaptive buffer causes the first power transistor to be on through a range of output current and to cause the second power transistor to be on through some, but not all, of the range of output current.

Abstract: A current sensing circuit includes a pass transistor, a first sense transistor, a second sense transistor, a driver circuit, and sense circuitry. The driver circuit coupled to, and configured to generate a drive signal to control, the pass transistor, the first sense transistor, and the second sense transistor. The sense circuitry coupled to the pass transistor, the first sense transistor, and the second sense transistor. The sense circuitry includes a first sense circuit and a second sense circuit. The first sense circuit is configured to generate an output current proportional to a current flowing in the pass transistor. The second sense circuit is coupled to the driver circuit and is configured to set the drive signal to a predetermined voltage responsive to a voltage across the pass transistor being less than a threshold voltage.

Abstract: A tool is configured to determine process and service strengths as related to the accomplishment of one or more objectives. One or more processes include associated process information relating to various process attributes. The tool may execute a plurality of scoring modules to produce scores representative of strengths of processes and services as related to the accomplishment of the objectives. The scores may be used to identify processes for adjustment having a maximum impact on the scores.