Patents by Inventor Saurabh SETHI

Saurabh SETHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250217051
    Abstract: This disclosure provides systems, methods, and devices for memory systems that support merged memory commands for improved bus utilization in volatile memory. In a first aspect, a method of performing operations on a memory module includes receiving, from a host device by a memory controller coupled to a memory module through a first channel and configured to access data stored in the memory module through the first channel, a merged command for performing at least a precharge operation, a refresh operation, and an activate operation on one or more rows of the memory module and performing the precharge operation, the refresh operation, and the activate operation in accordance with receipt of the merged command. Other aspects and features are also claimed and described.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 3, 2025
    Inventors: Madhukar Reddy N, Amulya Srinivasan Margasahayam, Vasantha Kumar Bandur Puttappa, Abhay Raj, Saurabh Sethi
  • Publication number: 20250104758
    Abstract: Various embodiments include methods for implementing a multi-bank memory refresh command on memory devices. A memory controller may select a number of memory banks to refresh in a refresh cycle, select a first memory bank to refresh, and send the memory device a multi-bank of memory refresh command that encodes the number of memory banks and the first memory bank to refresh. The memory device may recognize the multi-bank memory refresh command based on signals received over a number of clock cycles, decode the command to identify the number of memory banks to refreshed and the first memory bank to refresh, and then refresh the identified number of memory banks starting from the identified first memory bank.
    Type: Application
    Filed: September 22, 2023
    Publication date: March 27, 2025
    Inventors: Saurabh SETHI, Vasantha Kumar Bandur PUTTAPPA, Amulya Srinivasan MARGASAHAYAM, Madhukar Reddy N, Abhay RAJ
  • Patent number: 12106793
    Abstract: Aspects of the present disclosure are directed to techniques and procedures for reducing memory (e.g., DRAM) access latency (e.g., read latency, write latency) due to memory refreshes. In some aspects, a memory refresh scheduling algorithm can take into account of memory access batching (e.g., read batch, write batch). In some aspects, a refresh scheduling algorithm can schedule more or prioritize refreshes to occur during a write batch to reduce memory read access latency because fewer refreshes are scheduled during memory read access. The techniques can be adapted to reduce write latency.
    Type: Grant
    Filed: December 14, 2022
    Date of Patent: October 1, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Saurabh Sethi, Madhukar Reddy N, Vasantha Kumar Bandur Puttappa, Amulya Srinivasan Margasahayam
  • Publication number: 20240203476
    Abstract: Aspects of the present disclosure are directed to techniques and procedures for reducing memory (e.g., DRAM) access latency (e.g., read latency, write latency) due to memory refreshes. In some aspects, a memory refresh scheduling algorithm can take into account of memory access batching (e.g., read batch, write batch). In some aspects, a refresh scheduling algorithm can schedule more or prioritize refreshes to occur during a write batch to reduce memory read access latency because fewer refreshes are scheduled during memory read access. The techniques can be adapted to reduce write latency.
    Type: Application
    Filed: December 14, 2022
    Publication date: June 20, 2024
    Inventors: Saurabh SETHI, Madhukar Reddy N, Vasantha Kumar Bandur PUTTAPPA, Amulya Srinivasan MARGASAHAYAM