Patents by Inventor Saurabh SETHI

Saurabh SETHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12106793
    Abstract: Aspects of the present disclosure are directed to techniques and procedures for reducing memory (e.g., DRAM) access latency (e.g., read latency, write latency) due to memory refreshes. In some aspects, a memory refresh scheduling algorithm can take into account of memory access batching (e.g., read batch, write batch). In some aspects, a refresh scheduling algorithm can schedule more or prioritize refreshes to occur during a write batch to reduce memory read access latency because fewer refreshes are scheduled during memory read access. The techniques can be adapted to reduce write latency.
    Type: Grant
    Filed: December 14, 2022
    Date of Patent: October 1, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Saurabh Sethi, Madhukar Reddy N, Vasantha Kumar Bandur Puttappa, Amulya Srinivasan Margasahayam
  • Publication number: 20240203476
    Abstract: Aspects of the present disclosure are directed to techniques and procedures for reducing memory (e.g., DRAM) access latency (e.g., read latency, write latency) due to memory refreshes. In some aspects, a memory refresh scheduling algorithm can take into account of memory access batching (e.g., read batch, write batch). In some aspects, a refresh scheduling algorithm can schedule more or prioritize refreshes to occur during a write batch to reduce memory read access latency because fewer refreshes are scheduled during memory read access. The techniques can be adapted to reduce write latency.
    Type: Application
    Filed: December 14, 2022
    Publication date: June 20, 2024
    Inventors: Saurabh SETHI, Madhukar Reddy N, Vasantha Kumar Bandur PUTTAPPA, Amulya Srinivasan MARGASAHAYAM