Patents by Inventor Saurabh Shrivastava

Saurabh Shrivastava has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210034269
    Abstract: Embodiments of the present invention relate to multiple parallel lookups using a pool of shared memories by proper configuration of interconnection networks. The number of shared memories reserved for each lookup is reconfigurable based on the memory capacity needed by that lookup. The shared memories are grouped into homogeneous tiles. Each lookup is allocated a set of tiles based on the memory capacity needed by that lookup. The tiles allocated for each lookup do not overlap with other lookups such that all lookups can be performed in parallel without collision. Each lookup is reconfigurable to be either hash-based or direct-access. The interconnection networks are programed based on how the tiles are allocated for each lookup.
    Type: Application
    Filed: August 18, 2020
    Publication date: February 4, 2021
    Inventors: Anh T. Tran, Gerald Schmidt, Tsahi Daniel, Saurabh Shrivastava
  • Publication number: 20210027104
    Abstract: Systems and methods for annotated data collection in an electronic messaging platform. One example system includes a machine learning database and an electronic processor communicatively coupled to the machine learning database. The electronic processor is configured to receive a plurality of electronic messages. The electronic processor is configured to select a sample message set from the plurality of electronic messages. The electronic processor is configured to add an actionable message to each electronic message of the sample message set. The electronic processor is configured to receive an actionable message selection from an electronic messaging client. The actionable message selection includes a user label indication and a message identifier. The electronic processor is configured to store the actionable message selection in the machine learning database.
    Type: Application
    Filed: July 25, 2019
    Publication date: January 28, 2021
    Inventors: Saurabh SHRIVASTAVA, Rajath Kumar RAVI, Saheel Ram GODHANE, Prateek AGRAWAL, Manvendra Pramendra KUMAR, Bikash Ranjan SWAIN, T Guru Pradeep REDDY
  • Publication number: 20200351206
    Abstract: Embodiments of the present invention relate to a centralized network analytic device, the centralized network analytic device efficiently uses on-chip memory to flexibly perform counting, traffic rate monitoring and flow sampling. The device includes a pool of memory that is shared by all cores and packet processing stages of each core. The counting, the monitoring and the sampling are all defined through software allowing for greater flexibility and efficient analytics in the device. In some embodiments, the device is a network switch.
    Type: Application
    Filed: May 15, 2020
    Publication date: November 5, 2020
    Inventors: Weihuang Wang, Gerald Schmidt, Tsahi Daniel, Saurabh Shrivastava
  • Patent number: 10782907
    Abstract: Embodiments of the present invention relate to multiple parallel lookups using a pool of shared memories by proper configuration of interconnection networks. The number of shared memories reserved for each lookup is reconfigurable based on the memory capacity needed by that lookup. The shared memories are grouped into homogeneous tiles. Each lookup is allocated a set of tiles based on the memory capacity needed by that lookup. The tiles allocated for each lookup do not overlap with other lookups such that all lookups can be performed in parallel without collision. Each lookup is reconfigurable to be either hash-based or direct-access. The interconnection networks are programmed based on how the tiles are allocated for each lookup.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: September 22, 2020
    Assignee: MARVELL ASIA PTE, LTD.
    Inventors: Anh T. Tran, Gerald Schmidt, Tsahi Daniel, Saurabh Shrivastava
  • Patent number: 10680957
    Abstract: Embodiments of the present invention relate to a centralized network analytic device, the centralized network analytic device efficiently uses on-chip memory to flexibly perform counting, traffic rate monitoring and flow sampling. The device includes a pool of memory that is shared by all cores and packet processing stages of each core. The counting, the monitoring and the sampling are all defined through software allowing for greater flexibility and efficient analytics in the device. In some embodiments, the device is a network switch.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: June 9, 2020
    Assignee: Cavium International
    Inventors: Weihuang Wang, Gerald Schmidt, Tsahi Daniel, Saurabh Shrivastava
  • Patent number: 10564987
    Abstract: A system, such as a system of a computing resource service provider, tracks infrastructure-level changes to execution environments caused by or otherwise associated with activity associated with executable code. In one embodiment, the activity is associated with development and/or testing of the executable code, and a monitoring service generates a log of changes to the associated infrastructure caused by the activity over a designated period of time. The log of changes is used to generate a template that in turn causes configuration of a target execution environment in accordance with the monitored changes.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: February 18, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Julien D. Lépine, Damián Arregui Melmann, Saurabh Shrivastava
  • Publication number: 20200043232
    Abstract: A method and system for exporting a 3D object in an application to a file having a 3D file format is disclosed. The method includes a receiving a request for exporting a 3D object in an application to a file having a 3D file format where the 3D object includes a plurality of components. Upon receiving the request, the components are examined to determine if any of them are a 2D text component. When it is determined that at least one of the components is a 2D text component, a database may be referenced to identify a text character that corresponds to the 2D text component, before replacing the 2D text component with a corresponding 3D model in the file.
    Type: Application
    Filed: November 29, 2018
    Publication date: February 6, 2020
    Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Prateek AGRAWAL, Bikash Ranjan SWAIN, Hindol ADHYA, Alok AGRAWAL, Saurabh SHRIVASTAVA
  • Patent number: 10499532
    Abstract: An infrastructure floor tile for supporting and positioning a server rack in a datacenter includes a body including top, bottom and side surfaces and a first alignment surface on the top surface. The first alignment surface includes at least one of a projection and a recess. When a server rack is positioned on the first alignment surface of the infrastructure floor tile, the server rack is aligned by the first alignment surface relative to the body. N horizontal channels extend from one of the side surfaces to an opposite one of the side surfaces, where N is an integer greater than one. N vertical channels extending from the top surface of the body to the N horizontal channels, respectively. Power, cooling fluid and/or data lines are connected to the server rack through at least one of the N horizontal channels and at least one of the N vertical channels.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: December 3, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Nicholas Andrew Keehn, Winston Allen Saunders, Sean James, Saurabh Shrivastava
  • Publication number: 20190357377
    Abstract: An infrastructure floor tile for supporting and positioning a server rack in a datacenter includes a body including top, bottom and side surfaces and a first alignment surface on the top surface. The first alignment surface includes at least one of a projection and a recess. When a server rack is positioned on the first alignment surface of the infrastructure floor tile, the server rack is aligned by the first alignment surface relative to the body. N horizontal channels extend from one of the side surfaces to an opposite one of the side surfaces, where N is an integer greater than one. N vertical channels extending from the top surface of the body to the N horizontal channels, respectively. Power, cooling fluid and/or data lines are connected to the server rack through at least one of the N horizontal channels and at least one of the N vertical channels.
    Type: Application
    Filed: May 16, 2018
    Publication date: November 21, 2019
    Inventors: Nicholas Andrew KEEHN, Winston Allen SAUNDERS, Sean JAMES, Saurabh SHRIVASTAVA
  • Publication number: 20180203639
    Abstract: Embodiments of the present invention relate to multiple parallel lookups using a pool of shared memories by proper configuration of interconnection networks. The number of shared memories reserved for each lookup is reconfigurable based on the memory capacity needed by that lookup. The shared memories are grouped into homogeneous tiles. Each lookup is allocated a set of tiles based on the memory capacity needed by that lookup. The tiles allocated for each lookup do not overlap with other lookups such that all lookups can be performed in parallel without collision. Each lookup is reconfigurable to be either hash-based or direct-access. The interconnection networks are programed based on how the tiles are allocated for each lookup.
    Type: Application
    Filed: March 16, 2018
    Publication date: July 19, 2018
    Inventors: Anh T. Tran, Gerald Schmidt, Tsahi Daniel, Saurabh Shrivastava
  • Patent number: 9952800
    Abstract: Embodiments of the present invention relate to multiple parallel lookups using a pool of shared memories by proper configuration of interconnection networks. The number of shared memories reserved for each lookup is reconfigurable based on the memory capacity needed by that lookup. The shared memories are grouped into homogeneous tiles. Each lookup is allocated a set of tiles based on the memory capacity needed by that lookup. The tiles allocated for each lookup do not overlap with other lookups such that all lookups can be performed in parallel without collision. Each lookup is reconfigurable to be either hash-based or direct-access. The interconnection networks are programmed based on how the tiles are allocated for each lookup.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: April 24, 2018
    Assignee: Cavium, Inc.
    Inventors: Anh T. Tran, Gerald Schmidt, Tsahi Daniel, Saurabh Shrivastava
  • Patent number: 9952799
    Abstract: Embodiments of the present invention relate to multiple parallel lookups using a pool of shared memories by proper configuration of interconnection networks. The number of shared memories reserved for each lookup is reconfigurable based on the memory capacity needed by that lookup. The shared memories are grouped into homogeneous tiles. Each lookup is allocated a set of tiles based on the memory capacity needed by that lookup. The tiles allocated for each lookup do not overlap with other lookups such that all lookups can be performed in parallel without collision. Each lookup is reconfigurable to be either hash-based or direct-access. The interconnection networks are programmed based on how the tiles are allocated for each lookup.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: April 24, 2018
    Assignee: Cavium, Inc.
    Inventors: Anh T. Tran, Gerald Schmidt, Tsahi Daniel, Saurabh Shrivastava
  • Publication number: 20170242619
    Abstract: Embodiments of the present invention relate to multiple parallel lookups using a pool of shared memories by proper configuration of interconnection networks. The number of shared memories reserved for each lookup is reconfigurable based on the memory capacity needed by that lookup. The shared memories are grouped into homogeneous tiles. Each lookup is allocated a set of tiles based on the memory capacity needed by that lookup. The tiles allocated for each lookup do not overlap with other lookups such that all lookups can be performed in parallel without collision. Each lookup is reconfigurable to be either hash-based or direct-access. The interconnection networks are programed based on how the tiles are allocated for each lookup.
    Type: Application
    Filed: March 1, 2017
    Publication date: August 24, 2017
    Inventors: Anh T. Tran, Gerald Schmidt, Tsahi Daniel, Saurabh Shrivastava
  • Publication number: 20170242618
    Abstract: Embodiments of the present invention relate to multiple parallel lookups using a pool of shared memories by proper configuration of interconnection networks. The number of shared memories reserved for each lookup is reconfigurable based on the memory capacity needed by that lookup. The shared memories are grouped into homogeneous tiles. Each lookup is allocated a set of tiles based on the memory capacity needed by that lookup. The tiles allocated for each lookup do not overlap with other lookups such that all lookups can be performed in parallel without collision. Each lookup is reconfigurable to be either hash-based or direct-access. The interconnection networks are programed based on how the tiles are allocated for each lookup.
    Type: Application
    Filed: March 1, 2017
    Publication date: August 24, 2017
    Inventors: Anh T. Tran, Gerald Schmidt, Tsahi Daniel, Saurabh Shrivastava
  • Patent number: 9620213
    Abstract: Embodiments of the present invention relate to multiple parallel lookups using a pool of shared memories by proper configuration of interconnection networks. The number of shared memories reserved for each lookup is reconfigurable based on the memory capacity needed by that lookup. The shared memories are grouped into homogeneous tiles. Each lookup is allocated a set of tiles based on the memory capacity needed by that lookup. The tiles allocated for each lookup do not overlap with other lookups such that all lookups can be performed in parallel without collision. Each lookup is reconfigurable to be either hash-based or direct-access. The interconnection networks are programmed based on how the tiles are allocated for each lookup.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: April 11, 2017
    Assignee: Cavium, Inc.
    Inventors: Anh T. Tran, Gerald Schmidt, Tsahi Daniel, Saurabh Shrivastava
  • Publication number: 20150350089
    Abstract: Embodiments of the present invention relate to a centralized network analytic device, the centralized network analytic device efficiently uses on-chip memory to flexibly perform counting, traffic rate monitoring and flow sampling. The device includes a pool of memory that is shared by all cores and packet processing stages of each core. The counting, the monitoring and the sampling are all defined through software allowing for greater flexibility and efficient analytics in the device. In some embodiments, the device is a network switch.
    Type: Application
    Filed: May 28, 2014
    Publication date: December 3, 2015
    Applicant: XPLIANT, Inc
    Inventors: Weihuang Wang, Gerald Schmidt, Tsahi Daniel, Saurabh Shrivastava
  • Publication number: 20150187419
    Abstract: Embodiments of the present invention relate to multiple parallel lookups using a pool of shared memories by proper configuration of interconnection networks. The number of shared memories reserved for each lookup is reconfigurable based on the memory capacity needed by that lookup. The shared memories are grouped into homogeneous tiles. Each lookup is allocated a set of tiles based on the memory capacity needed by that lookup. The tiles allocated for each lookup do not overlap with other lookups such that all lookups can be performed in parallel without collision. Each lookup is reconfigurable to be either hash-based or direct-access. The interconnection networks are programmed based on how the tiles are allocated for each lookup.
    Type: Application
    Filed: December 27, 2013
    Publication date: July 2, 2015
    Applicant: XPLIANT, INC.
    Inventors: Anh T. Tran, Gerald Schmidt, Tsahi Daniel, Saurabh Shrivastava
  • Patent number: 8942679
    Abstract: A method is disclosed in which a server generates and transmits a reply to a mobile device via a wireless communication link in response to receiving a request from a mobile device. The reply includes first pattern information and data elements retrieved from a logical data model. The mobile device renders a first page on a screen thereof in response to receiving the reply. The first page includes visual representations of the data elements, and the first page presents the visual representations in a first pattern corresponding to the first pattern information.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: January 27, 2015
    Assignee: Oracle International Corporation
    Inventors: Saurabh Shrivastava, Sridhar Tadepalli, Wayne Carter, Rahim Yaseen
  • Publication number: 20130243002
    Abstract: A method, apparatus and system for processing control packets in a routing device by comparing the timestamp of the received packets to an expiry time associated with a first neighbor node in a suspended animation (SA) list and in response to the timestamp being more than the expiry time, removing all the neighbor nodes having an expiry time less than that of the timestamp.
    Type: Application
    Filed: March 19, 2012
    Publication date: September 19, 2013
    Inventor: Saurabh Shrivastava
  • Publication number: 20120109913
    Abstract: A method and system for efficiently processing regular expressions associated with new BGP packets uses the caches results of prior processing of regular expressions associated with a prior matching BGP packet within the same epoch.
    Type: Application
    Filed: March 18, 2011
    Publication date: May 3, 2012
    Inventors: Abhay C. Rajure, Saurabh Shrivastava