Patents by Inventor Sauvik Chowdhury
Sauvik Chowdhury has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240055511Abstract: A semiconductor device includes a first source region, a first sidewall body region, a gate region, a second source region and a link region formed in a substrate of a first conductivity type. The first source region and the second source region may be of the first conductivity type while the first sidewall body region and the link region may be of a second conductivity type opposite to the first conductivity type. The link region and the gate region are respectively disposed at a first side and a second side of the first source region. The first sidewall body region may be disposed below or underneath the first source region.Type: ApplicationFiled: August 8, 2023Publication date: February 15, 2024Inventors: Vipindas Pala, Sauvik Chowdhury
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Publication number: 20240055514Abstract: A method for manufacturing a semiconductor device includes preparing a substrate of a first conductivity type having a drain region, forming a first source region and a second source region of the first conductivity type in the substrate separated from each other, and forming a gate trench of a gate region disposed closely next to or in adjoining neighbor to the first source region. The method may further include forming a first sidewall body region of a second conductivity type to separate the first source region from the second source region, forming a link region of the second conductivity type such that the link region and the gate trench are disposed spatially opposite to each other, forming a gate insulation layer to coat and line sidewalls and a bottom of the gate trench, and using a gate conductive material to fill the gate trench.Type: ApplicationFiled: August 8, 2023Publication date: February 15, 2024Inventors: Vipindas Pala, Sauvik Chowdhury
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Publication number: 20240055473Abstract: A semiconductor device includes a first source region, a first sidewall body region, a gate region, a second source region and a link region formed in a substrate of a first conductivity type. The first source region and the second source region may be of the first conductivity type while the first sidewall body region and the link region may be of a second conductivity type opposite to the first conductivity type. The link region and the gate region are respectively disposed at a first side and a second side of the first source region. The first sidewall body region may be disposed below or underneath the first source region.Type: ApplicationFiled: August 8, 2023Publication date: February 15, 2024Inventors: Vipindas Pala, Sauvik Chowdhury
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Publication number: 20240055513Abstract: A method for manufacturing a semiconductor device includes preparing a substrate of a first conductivity type having a drain region, forming a first source region and a second source region of the first conductivity type in the substrate separated from each other, and forming a gate trench of a gate region disposed closely next to or in adjoining neighbor to the first source region. The method may further include forming a first sidewall body region of a second conductivity type to separate the first source region from the second source region, forming a link region of the second conductivity type such that the link region and the gate trench are disposed spatially opposite to each other, forming a gate insulation layer to coat and line sidewalls and a bottom of the gate trench, and using a gate conductive material to fill the gate trench.Type: ApplicationFiled: August 8, 2023Publication date: February 15, 2024Inventors: Vipindas Pala, Sauvik Chowdhury
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Publication number: 20240055512Abstract: A semiconductor device includes a first source region, a first sidewall body region, a gate region, a second source region and a link region formed in a substrate of a first conductivity type. The first source region and the second source region may be of the first conductivity type while the first sidewall body region and the link region may be of a second conductivity type opposite to the first conductivity type. The link region and the gate region are respectively disposed at a first side and a second side of the first source region. The first sidewall body region may be disposed below or underneath the first source region.Type: ApplicationFiled: August 8, 2023Publication date: February 15, 2024Inventors: Vipindas Pala, Sauvik Chowdhury
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Publication number: 20230282732Abstract: A process of forming an electronic device can form an accumulation channel or an integrated diode by selective doping parts of a workpiece. In an embodiment, a doped region can be formed by implanting a sidewall of a body region. In another embodiment, a doped region can correspond to a remaining portion of a semiconductor layer after forming another doped region by implanting into a contact opening. The accumulation channel or the integrated diode can lower the barrier for a body diode turn-on. Reduced stored charge and QRR may be achieved, leading to lower switching losses.Type: ApplicationFiled: March 2, 2022Publication date: September 7, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Balaji PADMANABHAN, Zia HOSSAIN, Dean E. PROBST, Peter A. BURKE, Sauvik CHOWDHURY
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Publication number: 20230253468Abstract: In one general aspect, an apparatus can include a substrate having a semiconductor region, and a trench defined in the semiconductor region and having a sidewall. The apparatus can include a shield electrode disposed in the trench and insulated from the sidewall of the trench by a shield dielectric, the shield dielectric having a low-k dielectric portion and a high-k dielectric portion. The apparatus can include a gate electrode disposed in the trench and at least partially surrounded by a gate dielectric, and an inter-electrode dielectric disposed between the shield electrode and the gate electrode.Type: ApplicationFiled: February 9, 2022Publication date: August 10, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Zia HOSSAIN, Balaji PADMANABHAN, Christopher Lawrence REXER, Gordon M. GRIVNA, Sauvik CHOWDHURY
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Publication number: 20230113308Abstract: In a general aspect, a vertical transistor can include a semiconductor region of a first conductivity type, and a plurality of perpendicularly intersecting trenches having a shielded gate structure of the vertical transistor disposed therein. A mesa of the semiconductor region can be defined by the plurality of perpendicularly intersecting trenches. The mesa can include a proximal end portion having a first doping concentration of the first conductivity type, a distal end portion having the first doping concentration of the first conductivity type, and a central portion disposed between the proximal end portion and the distal end portion. The central portion can have a second doping concentration of the first conductivity type that is less than the first doping concentration.Type: ApplicationFiled: October 5, 2022Publication date: April 13, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Balaji PADMANABHAN, Prasad VENKATRAMAN, Sauvik CHOWDHURY
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Publication number: 20220310813Abstract: A device includes a mesa disposed between a pair of vertical trenches in a semiconductor substrate. A gate electrode is disposed in each of the pair of vertical trenches, and a shield electrode is disposed below each of the gate electrodes in the pair of vertical trenches. The device further includes a bridge connection trench traversing the mesa. The bridge connection trench is in fluid communication with each of the pair of vertical trenches. A bridge shield electrode is disposed in the bridge connection trench and is coupled to the shield electrode disposed below each of the gate electrodes in the pair of vertical trenches.Type: ApplicationFiled: March 2, 2022Publication date: September 29, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Zia HOSSAIN, Balaji PADMANABHAN, Sauvik CHOWDHURY
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Publication number: 20220254889Abstract: An electronic device can include a substrate, an active region of a transistor, and a shield electrode. The substrate can define a trench and include a mesa adjacent to the trench, and the shield electrode can be within the trench. In an embodiment, the electronic device can further include an active region of a transistor within the mesa and an insulating layer including a thicker section and a thinner section closer to a bottom of the trench. In another embodiment, the electronic device can include a body region and a doped region within the mesa and spaced apart from the body region by a semiconductor region. The doped region can have a dopant concentration that is higher than a dopant concentration of the semiconductor region and a portion of the substrate underlying the doped region.Type: ApplicationFiled: April 26, 2022Publication date: August 11, 2022Applicant: Semiconductor Components Industries, LLCInventors: Zia Hossain, Joseph Andrew Yedinak, Sauvik Chowdhury, Muh-Ling Ger
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Patent number: 11342424Abstract: An electronic device can include a substrate, an active region of a transistor, and a shield electrode. The substrate can define a trench and include a mesa adjacent to the trench, and the shield electrode can be within the trench. In an embodiment, the electronic device can further include an active region of a transistor within the mesa and an insulating layer including a thicker section and a thinner section closer to a bottom of the trench. In another embodiment, the electronic device can include a body region and a doped region within the mesa and spaced apart from the body region by a semiconductor region. The doped region can have a dopant concentration that is higher than a dopant concentration of the semiconductor region and a portion of the substrate underlying the doped region.Type: GrantFiled: April 13, 2020Date of Patent: May 24, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Zia Hossain, Joseph Andrew Yedinak, Sauvik Chowdhury, Muh-Ling Ger
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Patent number: 11309414Abstract: Metal-Oxide-Semiconductor (MOS) controlled semiconductor devices and methods of making the devices are provided. The devices include a gate which controls current flow through channel regions positioned between source/emitter and drain regions of the device. The devices include a gate oxide layer having a variable thickness. The thickness of the gate oxide layer under the edge of the gate and over the source/emitter regions is different than the thickness over the channel regions of the device. The oxide layer thickness near the edge of the gate can be greater than the oxide layer thickness over the channel regions. The source/emitter regions can be implanted to provide enhanced oxide growth during gate oxide formation. The source/emitter region can include regions that are implanted to provide enhanced oxide growth during gate oxide formation and regions which do not provide enhanced oxide growth during gate oxide formation. The devices can be SiC devices such as SiC MOSFETs and SiC IGBTs.Type: GrantFiled: February 6, 2020Date of Patent: April 19, 2022Assignee: Monolith Semiconductor Inc.Inventors: Kevin Matocha, Sauvik Chowdhury, Kiran Chatty, John Nowak
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Publication number: 20210320178Abstract: An electronic device can include a substrate, an active region of a transistor, and a shield electrode. The substrate can define a trench and include a mesa adjacent to the trench, and the shield electrode can be within the trench. In an embodiment, the electronic device can further include an active region of a transistor within the mesa and an insulating layer including a thicker section and a thinner section closer to a bottom of the trench. In another embodiment, the electronic device can include a body region and a doped region within the mesa and spaced apart from the body region by a semiconductor region. The doped region can have a dopant concentration that is higher than a dopant concentration of the semiconductor region and a portion of the substrate underlying the doped region.Type: ApplicationFiled: April 13, 2020Publication date: October 14, 2021Applicant: Semiconductor Components Industries, LLCInventors: Zia Hossain, Joseph Andrew Yedinak, Sauvik Chowdhury, Muh-Ling Ger
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Publication number: 20200176596Abstract: Metal-Oxide-Semiconductor (MOS) controlled semiconductor devices and methods of making the devices are provided. The devices include a gate which controls current flow through channel regions positioned between source/emitter and drain regions of the device. The devices include a gate oxide layer having a variable thickness. The thickness of the gate oxide layer under the edge of the gate and over the source/emitter regions is different than the thickness over the channel regions of the device. The oxide layer thickness near the edge of the gate can be greater than the oxide layer thickness over the channel regions. The source/emitter regions can be implanted to provide enhanced oxide growth during gate oxide formation. The source/emitter region can include regions that are implanted to provide enhanced oxide growth during gate oxide formation and regions which do not provide enhanced oxide growth during gate oxide formation. The devices can be SiC devices such as SiC MOSFETs and SiC IGBTs.Type: ApplicationFiled: February 6, 2020Publication date: June 4, 2020Applicant: Monolith Semiconductor Inc.Inventors: Kevin Matocha, Sauvik Chowdhury, Kiran Chatty, John Nowak
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Patent number: 10622472Abstract: Metal-Oxide-Semiconductor (MOS) controlled semiconductor devices and methods of making the devices are provided. The devices include a gate which controls current flow through channel regions positioned between source/emitter and drain regions of the device. The devices include a gate oxide layer having a variable thickness. The thickness of the gate oxide layer under the edge of the gate and over the source/emitter regions is different than the thickness over the channel regions of the device. The oxide layer thickness near the edge of the gate can be greater than the oxide layer thickness over the channel regions. The source/emitter regions can be implanted to provide enhanced oxide growth during gate oxide formation. The source/emitter region can include regions that are implanted to provide enhanced oxide growth during gate oxide formation and regions which do not provide enhanced oxide growth during gate oxide formation. The devices can be SiC devices such as SiC MOSFETs and SiC IGBTs.Type: GrantFiled: June 27, 2019Date of Patent: April 14, 2020Assignee: Monolith Semiconductor Inc.Inventors: Kevin Matocha, Sauvik Chowdhury, Kiran Chatty, John Nowak
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Publication number: 20190334025Abstract: Metal-Oxide-Semiconductor (MOS) controlled semiconductor devices and methods of making the devices are provided. The devices include a gate which controls current flow through channel regions positioned between source/emitter and drain regions of the device. The devices include a gate oxide layer having a variable thickness. The thickness of the gate oxide layer under the edge of the gate and over the source/emitter regions is different than the thickness over the channel regions of the device. The oxide layer thickness near the edge of the gate can be greater than the oxide layer thickness over the channel regions. The source/emitter regions can be implanted to provide enhanced oxide growth during gate oxide formation. The source/emitter region can include regions that are implanted to provide enhanced oxide growth during gate oxide formation and regions which do not provide enhanced oxide growth during gate oxide formation. The devices can be SiC devices such as SiC MOSFETs and SiC IGBTs.Type: ApplicationFiled: June 27, 2019Publication date: October 31, 2019Applicant: Monolith Semiconductor Inc.Inventors: Kevin Matocha, Sauvik Chowdhury, Kiran Chatty, John Nowak
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Patent number: 10361296Abstract: Metal-Oxide-Semiconductor (MOS) controlled semiconductor devices and methods of making the devices are provided. The devices include a gate which controls current flow through channel regions positioned between source/emitter and drain regions of the device. The devices include a gate oxide layer having a variable thickness. The thickness of the gate oxide layer under the edge of the gate and over the source/emitter regions is different than the thickness over the channel regions of the device. The oxide layer thickness near the edge of the gate can be greater than the oxide layer thickness over the channel regions. The source/emitter regions can be implanted to provide enhanced oxide growth during gate oxide formation. The source/emitter region can include regions that are implanted to provide enhanced oxide growth during gate oxide formation and regions which do not provide enhanced oxide growth during gate oxide formation. The devices can be SiC devices such as SiC MOSFETs and SiC IGBTs.Type: GrantFiled: June 29, 2017Date of Patent: July 23, 2019Assignee: Monolith Semiconductor Inc.Inventors: Kevin Matocha, Sauvik Chowdhury, Kiran Chatty, John Nowak
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Publication number: 20190006505Abstract: Metal-Oxide-Semiconductor (MOS) controlled semiconductor devices and methods of making the devices are provided. The devices include a gate which controls current flow through channel regions positioned between source/emitter and drain regions of the device. The devices include a gate oxide layer having a variable thickness. The thickness of the gate oxide layer under the edge of the gate and over the source/emitter regions is different than the thickness over the channel regions of the device. The oxide layer thickness near the edge of the gate can be greater than the oxide layer thickness over the channel regions. The source/emitter regions can be implanted to provide enhanced oxide growth during gate oxide formation. The source/emitter region can include regions that are implanted to provide enhanced oxide growth during gate oxide formation and regions which do not provide enhanced oxide growth during gate oxide formation. The devices can be SiC devices such as SiC MOSFETs and SiC IGBTs.Type: ApplicationFiled: June 29, 2017Publication date: January 3, 2019Inventors: Kevin Matocha, Sauvik Chowdhury, Kiran Chatty, John Nowak