Abstract: A synchronous test model (STM) and corresponding method capture the essential behavior of an asynchronous circuit under test. During operation of the method, (1) An STM for the asynchronous circuit is constructed assuming either a user-specified cycle length or an estimated cycle length; (2) a target fault list is created containing only faults in the asynchronous circuit, (3) test patterns are generated from the STM using a synchronous test generator; (4) the test patterns are translated into test sequences for the asynchronous circuit; and (5) the translated patterns are validated by fault simulation on the asynchronous circuit.

Abstract: A method of asynchronous circuit synthesis of initializable circuits from signal transition graphs (STG) that are either functionally initializable or functionally uninitializable is described. For functionally initializable cases, an initializable implementation can be achieved by proper assignment of don't care values. If the STG is not functionally initializable, the sources of uninitializability in the STG are identified and the STG is transformed into a functionally initializable specification by exploiting concurrency. Initializability is achieved at the expense of minimal removal of concurrency. Moreover, the transformation does not violate liveness and unique state coding properties of the STG. When the STG is functionally initializable or after an uninitializable STG is transformed to become functionally initializable the result is an initializable circuit design.