Abstract: In an algorithm for a logic synthesis procedure in which the gate conversion and optimization are conducted according to boundary conditions and optimizing conditions of input/output interfaces set for each unit, timing restriction of boundary sections can be obtained in a short period of time from an RTL description before the logic synthesis is executed. A boundary section is extracted from the RTL description before execution of logic synthesis. Using the boundary section, the logic synthesis and a design budget are executed to obtain timing restriction for the boundary section.