Patents by Inventor Saya Goud Langadi
Saya Goud Langadi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230221959Abstract: A processor is provided and includes a core that is configured to perform a decode operation on a multi-instruction packet comprising multiple instructions. The decode operation includes receiving the multi-instruction packet that includes first and second instructions. The first instruction includes a primary portion at a fixed first location and a secondary portion. The second instruction includes a primary portion at a fixed second location between the primary portion of the first instruction and the secondary portion of the first instruction. An operational code portion of the primary portion of each of the first and second instructions is accessed and decoded. An instruction packet including the primary and secondary portions of the first instruction is created, and a second instruction packet including the primary portion of the second instruction is created. The first and second instructions packets are dispatched to respective first and second functional units.Type: ApplicationFiled: February 27, 2023Publication date: July 13, 2023Inventors: Saya Goud Langadi, Venkatesh Natarajan, Alexander Tessarolo
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Patent number: 11663095Abstract: A circuit and method for verifying the operation of error checking circuitry. In one example, a circuit includes a memory, a first error checking circuit, a second error checking circuit, and a comparison circuit. The memory includes a data output. The first error checking circuit includes an input and an output. The input of the first error checking circuit is coupled to the data output of the memory. The second error checking circuit includes an input and an output. The input of the second error checking circuit is coupled to the data output of the memory. The comparison circuit includes a first input and a second input. The first input is coupled to the output of the first error checking circuit. The second input is coupled to the output of the second error checking circuit.Type: GrantFiled: July 12, 2021Date of Patent: May 30, 2023Assignee: Texas Instmments IncorporatedInventors: Saya Goud Langadi, Srinivasa Chakravarthy Bs
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Publication number: 20230068811Abstract: Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic having fifth inputs and fifth outputs, the third output and the fourth output coupled to the fifth inputs, and error detection logic having sixth inputs coupled to the fifth inputs.Type: ApplicationFiled: October 18, 2022Publication date: March 2, 2023Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Prasanth Viswanathan Pillai, Rajeev Suvarna, Saya Goud Langadi, Shailesh Ganapat Ghotgalkar
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Patent number: 11593110Abstract: A processor is provided and includes a core that is configured to perform a decode operation on a multi-instruction packet comprising multiple instructions. The decode operation includes receiving the multi-instruction packet that includes first and second instructions. The first instruction includes a primary portion at a fixed first location and a secondary portion. The second instruction includes a primary portion at a fixed second location between the primary portion of the first instruction and the secondary portion of the first instruction. An operational code portion of the primary portion of each of the first and second instructions is accessed and decoded. An instruction packet including the primary and secondary portions of the first instruction is created, and a second instruction packet including the primary portion of the second instruction is created. The first and second instructions packets are dispatched to respective first and second functional units.Type: GrantFiled: January 7, 2021Date of Patent: February 28, 2023Assignee: Texas Instruments IncorporatedInventors: Saya Goud Langadi, Venkatesh Natarajan, Alexander Tessarolo
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Publication number: 20220350699Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to determine memory access integrity based on feedback from memory. An example apparatus includes an access reconstruction controller including an output, a first input configured to be coupled to memory, and a second input configured to be coupled to a memory signal generator; a comparator including a first input coupled to the output of the access reconstruction controller, a second input configured to be coupled to an arbiter, and an output configured to be coupled to the arbiter; and a data integrity monitor including an input coupled to the second input of the comparator and configured to be coupled to the arbiter and an output coupled to the output of the comparator and configured to be coupled to the arbiter.Type: ApplicationFiled: July 18, 2022Publication date: November 3, 2022Inventors: Saya Goud Langadi, David Peter Foley
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Patent number: 11474151Abstract: Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic having fifth inputs and fifth outputs, the third output and the fourth output coupled to the fifth inputs, and error detection logic having sixth inputs coupled to the fifth inputs.Type: GrantFiled: December 30, 2020Date of Patent: October 18, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Prasanth Viswanathan Pillai, Rajeev Suvarna, Saya Goud Langadi, Shailesh Ganapat Ghotgalkar
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Patent number: 11392455Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to determine memory access integrity based on feedback from memory. An example apparatus includes an access reconstruction controller including an output, a first input configured to be coupled to memory, and a second input configured to be coupled to a memory signal generator; a comparator including a first input coupled to the output of the access reconstruction controller, a second input configured to be coupled to an arbiter, and an output configured to be coupled to the arbiter; and a data integrity monitor including an input coupled to the second input of the comparator and configured to be coupled to the arbiter and an output coupled to the output of the comparator and configured to be coupled to the arbiter.Type: GrantFiled: February 26, 2021Date of Patent: July 19, 2022Assignee: Texas Instruments IncorporatedInventors: Saya Goud Langadi, David Peter Foley
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Publication number: 20220214880Abstract: A processor is provided and includes a core that is configured to perform a decode operation on a multi-instruction packet comprising multiple instructions. The decode operation includes receiving the multi-instruction packet that includes first and second instructions. The first instruction includes a primary portion at a fixed first location and a secondary portion. The second instruction includes a primary portion at a fixed second location between the primary portion of the first instruction and the secondary portion of the first instruction. An operational code portion of the primary portion of each of the first and second instructions is accessed and decoded. An instruction packet including the primary and secondary portions of the first instruction is created, and a second instruction packet including the primary portion of the second instruction is created. The first and second instructions packets are dispatched to respective first and second functional units.Type: ApplicationFiled: January 7, 2021Publication date: July 7, 2022Inventors: Saya Goud Langadi, Venkatesh Natarajan, Alexander Tessarolo
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Publication number: 20220206065Abstract: Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic having fifth inputs and fifth outputs, the third output and the fourth output coupled to the fifth inputs, and error detection logic having sixth inputs coupled to the fifth inputs.Type: ApplicationFiled: December 30, 2020Publication date: June 30, 2022Inventors: Prasanth Viswanathan Pillai, Rajeev Suvarna, Saya Goud Langadi, Shailesh Ganapat Ghotgalkar
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Publication number: 20210342233Abstract: A circuit and method for verifying the operation of error checking circuitry. In one example, a circuit includes a memory, a first error checking circuit, a second error checking circuit, and a comparison circuit. The memory includes a data output. The first error checking circuit includes an input and an output. The input of the first error checking circuit is coupled to the data output of the memory. The second error checking circuit includes an input and an output. The input of the second error checking circuit is coupled to the data output of the memory. The comparison circuit includes a first input and a second input. The first input is coupled to the output of the first error checking circuit. The second input is coupled to the output of the second error checking circuit.Type: ApplicationFiled: July 12, 2021Publication date: November 4, 2021Inventors: Saya Goud LANGADI, JR., Srinivasa Chakravarthy BS
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Patent number: 11061783Abstract: A circuit and method for verifying the operation of error checking circuitry. In one example, a circuit includes a memory, a first error checking circuit, a second error checking circuit, and a comparison circuit. The memory includes a data output. The first error checking circuit includes an input and an output. The input of the first error checking circuit is coupled to the data output of the memory. The second error checking circuit includes an input and an output. The input of the second error checking circuit is coupled to the data output of the memory. The comparison circuit includes a first input and a second input. The first input is coupled to the output of the first error checking circuit. The second input is coupled to the output of the second error checking circuit.Type: GrantFiled: April 29, 2019Date of Patent: July 13, 2021Assignee: Texas Instruments IncorporatedInventors: Saya Goud Langadi, Srinivasa Chakravarthy Bs
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Publication number: 20200341869Abstract: A circuit and method for verifying the operation of error checking circuitry. In one example, a circuit includes a memory, a first error checking circuit, a second error checking circuit, and a comparison circuit. The memory includes a data output. The first error checking circuit includes an input and an output. The input of the first error checking circuit is coupled to the data output of the memory. The second error checking circuit includes an input and an output. The input of the second error checking circuit is coupled to the data output of the memory. The comparison circuit includes a first input and a second input. The first input is coupled to the output of the first error checking circuit. The second input is coupled to the output of the second error checking circuit.Type: ApplicationFiled: April 29, 2019Publication date: October 29, 2020Inventors: Saya Goud LANGADI, Srinivasa Chakravarthy BS
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Patent number: 10177747Abstract: A high resolution capture circuit and integrated circuit chip are disclosed and include first and second capture delay lines and an oscillator delay line. The oscillator delay line includes N timing delay elements sequentially coupled in a ring to generate a first clock signal. The first and second capture delay lines each include M capture delay elements sequentially coupled to pass a received signal in a first direction along a first signal path and to pass a clock signal in a second direction opposite to the first direction along a second signal path. The first capture delay line uses the first clock signal and the second capture delay line uses an inverse of the first clock signal. Each capture delay element forms a flip-flop and provides a one-bit output. All delay elements have essentially identical timing and M is equal to either N or to N/2.Type: GrantFiled: September 23, 2016Date of Patent: January 8, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Alexander Tessarolo, Saya Goud Langadi
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Patent number: 10062451Abstract: A schedulable memory scrubbing circuit and/or a known-state memory test circuit (collectively, background memory test apparatus (“BGMTA”)) are located on-chip with an integrated computing system. The BGMTA operates in parallel with a system CPU but shares a system bus with the CPU. The BGMTA sequentially reads one word at a time from a block of memory to be tested during system bus idle cycles. The schedulable memory scrubbing circuit embodiment tests on-chip parity/ECC memory arrays using memory controller-implemented parity or ECC error detection to trigger error handling interrupts. The known-state memory test circuit embodiment performs CRC calculations on known-state memory arrays as each data word is read sequentially. A final resulting CRC calculation value is compared to a known CRC value for the block, sometimes referred to as a “golden CRC.” If the two CRC values differ, a CRC error interrupt is triggered for servicing by the CPU.Type: GrantFiled: November 9, 2016Date of Patent: August 28, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Prasanth Viswanathan Pillai, Saya Goud Langadi
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Patent number: 9910803Abstract: A multi master system on chip (SoC) includes a plurality of masters comprising a first master and a second master, each configured to generate a request. A next state generator in the multi master SoC is configured to generate a next state of a round robin pointer in response to the request and a current state of the round robin pointer. The round robin pointer is configured to generate an enable signal to enable a priority encoder for the first master in response to the current state of the round robin pointer. Further, the next state of the round robin pointer is generated such that a priority is maintained for the first master until there is a request from the second master.Type: GrantFiled: June 17, 2014Date of Patent: March 6, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Saya Goud Langadi
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Publication number: 20170149418Abstract: A high resolution capture circuit and integrated circuit chip are disclosed and include first and second capture delay lines and an oscillator delay line. The oscillator delay line includes N timing delay elements sequentially coupled in a ring to generate a first clock signal. The first and second capture delay lines each include M capture delay elements sequentially coupled to pass a received signal in a first direction along a first signal path and to pass a clock signal in a second direction opposite to the first direction along a second signal path. The first capture delay line uses the first clock signal and the second capture delay line uses an inverse of the first clock signal. Each capture delay element forms a flip-flop and provides a one-bit output. All delay elements have essentially identical timing and M is equal to either N or to N/2.Type: ApplicationFiled: September 23, 2016Publication date: May 25, 2017Inventors: Alexander Tessarolo, Saya Goud Langadi
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Publication number: 20170133106Abstract: A schedulable memory scrubbing circuit and/or a known-state memory test circuit (collectively, background memory test apparatus (“BGMTA”)) are located on-chip with an integrated computing system. The BGMTA operates in parallel with a system CPU but shares a system bus with the CPU. The BGMTA sequentially reads one word at a time from a block of memory to be tested during system bus idle cycles. The schedulable memory scrubbing circuit embodiment tests on-chip parity/ECC memory arrays using memory controller-implemented parity or ECC error detection to trigger error handling interrupts. The known-state memory test circuit embodiment performs CRC calculations on known-state memory arrays as each data word is read sequentially. A final resulting CRC calculation value is compared to a known CRC value for the block, sometimes referred to as a “golden CRC.” If the two CRC values differ, a CRC error interrupt is triggered for servicing by the CPU.Type: ApplicationFiled: November 9, 2016Publication date: May 11, 2017Inventors: Prasanth Viswanathan Pillai, Saya Goud Langadi
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Patent number: 9645964Abstract: A pipeline communication system includes a master and a plurality of slaves configured to communicate with each other. Each of the plurality of slaves includes a memory, and is configured to generate a first ready signal and a second ready signal. The first ready signal is configured to be provided only to the master and the second ready signal is configured to be provided only to each of the plurality of slaves. The second ready signal is generated independent of the error check in each of the plurality of slaves.Type: GrantFiled: April 24, 2015Date of Patent: May 9, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Saya Goud Langadi
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Publication number: 20150227488Abstract: A pipeline communication system includes a master and a plurality of slaves configured to communicate with each other. Each of the plurality of slaves includes a memory, and is configured to generate a first ready signal and a second ready signal. The first ready signal is configured to be provided only to the master and the second ready signal is configured to be provided only to each of the plurality of slaves. The second ready signal is generated independent of the error check in each of the plurality of slaves.Type: ApplicationFiled: April 24, 2015Publication date: August 13, 2015Inventor: Saya Goud Langadi
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Patent number: 9021170Abstract: A pipeline communication system includes a master and a plurality of slaves configured to communicate with each other. Each of the plurality of slaves includes a memory, and is configured to generate a first ready signal and a second ready signal. The first ready signal is configured to be provided only to the master and the second ready signal is configured to be provided only to each of the plurality of slaves. The second ready signal is generated independent of the error check in each of the plurality of slaves.Type: GrantFiled: June 22, 2012Date of Patent: April 28, 2015Assignee: Texas Instruments IncorporatedInventor: Saya Goud Langadi