Patents by Inventor Sayak Dutta Gupta

Sayak Dutta Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10840348
    Abstract: The present disclosure provides an improved enhancement mode field effect transistor (FET) having an oxide (AlxTi1-xO) emulating p-type gate. The present disclosure provides a novel enhancement mode High Electron Mobility Transistor (HEMT) structure with AlxTi1-xO Gate Oxide Engineering as Replacement of p-GaN Gate. In an aspect, the present disclosure provides a hybrid gate stack that combines p-GaN technology with the proposed oxide for e-mode operation. The HEMT structure with AlxTi1-xO Gate oxide provides a threshold voltage tuning from negative to positive by changing p-doping composition. Using a developed p-type oxide, e-mode device shows ON current ˜400 mA/mm, sub-threshold slope of 73 mV/dec, Ron=8.9 ?mm, interface trap density <1010 mm?2eV?1 and gate leakage below 200 nA/mm at the OFF-state breakdown.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: November 17, 2020
    Assignee: Indian Institute of Science
    Inventors: Mayank Shrivastava, Sayak Dutta Gupta, Ankit Soni, Srinivasan Raghavan, Navakanta Bhat
  • Publication number: 20190067440
    Abstract: The present disclosure provides an improved enhancement mode field effect transistor (FET) having an oxide (AlxTi1-xO) emulating p-type gate. The present disclosure provides a novel enhancement mode High Electron Mobility Transistor (HEMT) structure with AlxTi1-xO Gate Oxide Engineering as Replacement of p-GaN Gate. In an aspect, the present disclosure provides a hybrid gate stack that combines p-GaN technology with the proposed oxide for e-mode operation. The HEMT structure with AlxTi1-xO Gate oxide provides a threshold voltage tuning from negative to positive by changing p-doping composition. Using a developed p-type oxide, e-mode device shows ON current ˜400 mA/mm, sub-threshold slope of 73 mV/dec, Ron=8.9 ?mm, interface trap density <1010 mm?2eV?1 and gate leakage below 200 nA/mm at the OFF-state breakdown.
    Type: Application
    Filed: August 28, 2018
    Publication date: February 28, 2019
    Inventors: Mayank Shrivastava, Sayak Dutta Gupta, Ankit Soni, Srinivasan Raghavan, Navakanta Bhat