Abstract: An electronic device includes a sensor unit. The sensor unit includes a sensor and low power, low area sensor processing unit. The sensor processing unit performs an unsupervised machine learning processes to learn to recognize an activity or motion of the user or device. The user can request to learn the new activity. The sensor processing unit can request that the user remain stationary for a selected period of time before performing the activity. The sensor processing unit records sensor data while the user performs the activity and generates an activity template from the sensor data. The sensor processing can then infer when the user is performing the activity by comparing sensor signals to the activity template.

Abstract: An electronic device includes a sensor unit. The sensor unit includes a sensor and low power, low area sensor processing unit. The sensor processing unit performs an unsupervised machine learning processes to learn to recognize an activity or motion of the user or device. The user can request to learn the new activity. The sensor processing unit can request that the user remain stationary for a selected period of time before performing the activity. The sensor processing unit records sensor data while the user performs the activity and generates an activity template from the sensor data. The sensor processing can then infer when the user is performing the activity by comparing sensor signals to the activity template.

Abstract: A sensor system includes a plurality of inertial measurement units (IMU) and a control circuit. The control circuit is configured to receive sensor data from each of the inertial measurement units two alignment the timestamps of the sensor data, and to fuse the sensor data from the various IMUs. The control circuit detects whether the sensor data indicates a high degree movement or a low degree of movement and selects a high dynamic fusion process or a low dynamic fusion process based on the detected degree of movement.

Abstract: Disclosed herein are transistor arrangements of field-effect transistors with dual thickness gate dielectrics. An example transistor arrangement includes a semiconductor channel material, a source region and a drain region, provided in the semiconductor material, and a gate stack provided over a portion of the semiconductor material that is between the source region and the drain region. The gate stack has a thinner gate dielectric in a portion that is closer to the source region and a thicker gate dielectric in a portion that is closer to the drain region, which may effectively realize tunable ballast resistance integrated with the transistor arrangement and may help increase the breakdown voltage and/or decrease the gate leakage of the transistor.

Abstract: Disclosed herein are transistor arrangements of field-effect transistors with dual thickness gate dielectrics. An example transistor arrangement includes a semiconductor channel material, a source region and a drain region, provided in the semiconductor material, and a gate stack provided over a portion of the semiconductor material that is between the source region and the drain region. The gate stack has a thinner gate dielectric in a portion that is closer to the source region and a thicker gate dielectric in a portion that is closer to the drain region, which may effectively realize tunable ballast resistance integrated with the transistor arrangement and may help increase the breakdown voltage and/or decrease the gate leakage of the transistor.