Patents by Inventor Sayan Seal

Sayan Seal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250183119
    Abstract: Power semiconductor device assemblies are provided. In one example, a power semiconductor device assembly includes a semiconductor device package with one or more terminals. The semiconductor device package comprises one or more wide bandgap semiconductor die. The power semiconductor device assembly includes a support structure. The semiconductor device package is mounted onto the support structure. The power semiconductor device assembly includes an underfill structure. The underfill structure is at least partially on the support structure and the semiconductor device package.
    Type: Application
    Filed: November 30, 2023
    Publication date: June 5, 2025
    Inventor: Sayan Seal
  • Publication number: 20250149432
    Abstract: A packaged electronic device comprises a power semiconductor die that comprises a first terminal and a second terminal, a lead frame comprising a lower side and an upper side that comprises a die pad region, a first lead and a second lead, wherein the first lead is integral with the lead frame and electrically connected to the first terminal of the power semiconductor die through the lead frame, a dielectric substrate, and a thermally conductive adhesion layer on an upper side of the dielectric substrate.
    Type: Application
    Filed: January 8, 2025
    Publication date: May 8, 2025
    Inventors: Sayan Seal, Kuldeep Saxena, Devarajan Balaraman
  • Patent number: 12224233
    Abstract: A packaged electronic device comprises a power semiconductor die that comprises a first terminal and a second terminal, a lead frame comprising a lower side and an upper side that comprises a die pad region, a first lead and a second lead, wherein the first lead is integral with the lead frame and electrically connected to the first terminal of the power semiconductor die through the lead frame, a dielectric substrate, and a thermally conductive adhesion layer on an upper side of the dielectric substrate. The power semiconductor die is on the die pad region of the lead frame and the lead frame is on an upper side of the thermally conductive adhesion layer.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: February 11, 2025
    Assignee: Wolfspeed, Inc.
    Inventors: Sayan Seal, Kuldeep Saxena, Devarajan Balaraman
  • Publication number: 20230317670
    Abstract: A packaged electronic device comprises a power semiconductor die that includes a first terminal and a second terminal, a power substrate comprising a dielectric substrate having a first metal cladding layer on an upper surface thereof, an encapsulation covering the power semiconductor die and at least a portion of the power substrate, a first lead extending through the encapsulation that is electrically connected to the first terminal, and a second lead extending through the encapsulation that is electrically connected to the second terminal. The first terminal is bonded to the first lead via a first transient liquid phase solder joint.
    Type: Application
    Filed: March 29, 2022
    Publication date: October 5, 2023
    Inventor: Sayan Seal
  • Publication number: 20220238426
    Abstract: A packaged electronic device comprises a power semiconductor die that comprises a first terminal and a second terminal, a lead frame comprising a lower side and an upper side that comprises a die pad region, a first lead and a second lead, wherein the first lead is integral with the lead frame and electrically connected to the first terminal of the power semiconductor die through the lead frame, a dielectric substrate, and a thermally conductive adhesion layer on an upper side of the dielectric substrate.
    Type: Application
    Filed: January 27, 2021
    Publication date: July 28, 2022
    Inventors: Sayan Seal, Kuldeep Saxena, Devarajan Balaraman
  • Patent number: 10784235
    Abstract: A power module includes a case, a first terminal, a second terminal, and a number of silicon carbide semiconductor die. The case has a footprint less than 30 cm2. The silicon carbide semiconductor die are inside the case and coupled between the first terminal and the second terminal. The power module and the silicon carbide semiconductor die are configured such that in a first operating state the silicon carbide semiconductor die are capable of continuously blocking voltages greater than 650V between the first terminal and the second terminal, and in a second operating state the silicon carbide semiconductor die are capable of continuously passing currents greater than 200 A between the first terminal and the second terminal.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: September 22, 2020
    Assignee: Cree Fayetteville, Inc.
    Inventors: Brice McPherson, Sayan Seal, Zachary Cole, Jennifer Stabach, Brandon Passmore, Ty McNutt, Alexander B. Lostetter
  • Patent number: 10720380
    Abstract: A flip-chip wire bondless power device and method for using a two sided contact bare die power device as a single-connection-level power device. The device uses a top pad solder ball array for connecting a top pad electrically connected to the top contact of the bare die power device and a bottom pad solder ball array for connecting a bottom pad that is electrically through an electrically conductive bottom pad connector that is electrically connected to the bottom contact of the bare die power device using an electrically conductive die-attach material, the top pad and bottom pad, and thereby the top pad solder ball array and the bottom pad solder ball array are planar for flip chip mounting. A trench can be formed between the top pad and bottom pad for isolation and insulation purposes. A method of assembling a flip-chip wire bondless power device is also provided.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: July 21, 2020
    Inventors: Starlet R. Glover, Sayan Seal, H. Alan Mantooth
  • Publication number: 20190237439
    Abstract: A power module includes a case, a first terminal, a second terminal, and a number of silicon carbide semiconductor die. The case has a footprint less than 30 cm2. The silicon carbide semiconductor die are inside the case and coupled between the first terminal and the second terminal. The power module and the silicon carbide semiconductor die are configured such that in a first operating state the silicon carbide semiconductor die are capable of continuously blocking voltages greater than 650V between the first terminal and the second terminal, and in a second operating state the silicon carbide semiconductor die are capable of continuously passing currents greater than 200 A between the first terminal and the second terminal.
    Type: Application
    Filed: January 30, 2018
    Publication date: August 1, 2019
    Inventors: Brice McPherson, Sayan Seal, Zachary Cole, Jennifer Stabach, Brandon Passmore, Ty McNutt, Alexander B. Lostetter
  • Patent number: D909310
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: February 2, 2021
    Assignee: Cree, Fayetteville, Inc.
    Inventors: Brice McPherson, Sayan Seal, Zachary Cole, Jennifer Stabach, Brandon Passmore, Ty McNutt, Alexander B. Lostetter