Abstract: The present disclosure provides for encoding the signal using a window-based partitioned sequence of literals and then operating over this sequence to determine relevant periodic artifacts. A signal can be received, and then the signal can be abstracted to a sequence of literals. Repeating sub-sequences of literals can be identified in windows of time that increase in width until a repeating sub-sequence is found. Once a repeating sub-sequence is found, the window of time is shifted, and the process repeated. Once the temporal variations of the artifacts are known for the signal, the reference voltage at each of the time periods can be found by resampling the signal in different windows of time, finding temporary reference voltages that are means of samples in each window, determining the reference voltages for each time period, and then determining the DC reference based on a median of the list of reference values.

Abstract: Various embodiments disclosed herein provide for a glitch detection and level detection method that use information contained in the signal itself to determine at which resolution or granularity the glitch detection and level detection operates. In particular, the glitch detection method comprises defining a glitch in terms of a change in the area under the waveform which can serve to disambiguate glitches from noises and other transient side effects of level transmissions. Likewise, the level detection method uses an entropy-based metric to identify levels that are significant in context of the entire signal and not in absolute terms.

Abstract: A system and method utilized to receive an integrated circuit (IC) design and generating a graph based on a plurality of sub-circuits of the IC design. Further, one or more candidate sub-circuits are determined from the plurality of sub-circuits based on the graph. Additionally, one or more sub-circuits are identified from the one or more candidate sub-circuits based on a number of transistors and a number of edges within each of the plurality of sub-circuits. An indication of the identified one or more sub-circuits is provided.

Abstract: A system and method utilized to receive an integrated circuit (IC) design and generating a graph based on a plurality of sub-circuits of the IC design. Further, one or more candidate sub-circuits are determined from the plurality of sub-circuits based on the graph. Additionally, one or more sub-circuits are identified from the one or more candidate sub-circuits based on a number of transistors and a number of edges within each of the plurality of sub-circuits. An indication of the identified one or more sub-circuits is provided.