Patents by Inventor Sayed Mobin

Sayed Mobin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240213151
    Abstract: A semiconductor device includes semiconductor dies formed with through silicon vias (TSVs). The TSVs are coupled to contact pads in a surface of the semiconductor die by coils forming inductance loops at a number of contact pads. These inductance loops serve to distribute the capacitance at each bond pad along transmission lines, which distribution of the capacitance allows for a marked increase in read/write bandwidth for the semiconductor die.
    Type: Application
    Filed: July 17, 2023
    Publication date: June 27, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: John T. Contreras, Md. Sayed Mobin, Nagesh Vodrahalli, Narayanan Terizhandur Varadharajan
  • Publication number: 20240145424
    Abstract: A storage device includes a substrate of a memory package that includes a first pin pad, a controller mounted on the substrate and electrically connected to the first pin pad, the controller being configured to manage data communications on a data channel, and a first memory die. The first memory die includes a front pin pad electrically connected to the first pin pad of the substrate by way of a first bond wire, a rear pin pad, a conductor segment electrically connecting the front pin pad and the rear pin pad of the first memory die, and a plurality of memory cells configured to provide non-volatile storage accessible by way of the data channel.
    Type: Application
    Filed: July 19, 2023
    Publication date: May 2, 2024
    Inventors: John Contreras, Nagesh Vodrahalli, Md. Sayed Mobin
  • Publication number: 20240079318
    Abstract: A storage device includes a substrate of a memory package and a first memory die. The substrate includes a controller and a first pin pad, the first pin pad being electrically connected to the controller and defining a data channel for data communications. The first memory die includes a front pin pad electrically connected to the first pin pad of the substrate by way of a first bond wire, a rear pin pad, a redistribution layer electrically connecting the front pin pad and the rear pin pad of the first memory die, and a plurality of memory cells configured to provide non-volatile storage accessible by way of the data channel.
    Type: Application
    Filed: September 6, 2022
    Publication date: March 7, 2024
    Inventors: Md. Sayed Mobin, Nagesh Vodrahalli, Pranav Balachander, Narayanan Terizhandur V
  • Patent number: 11456022
    Abstract: The present disclosure generally relates to apparatuses and methods for transmission line termination. In one embodiment an apparatus includes a stack of uniform memory dies and a storage controller. Each uniform memory die in the stack of uniform memory dies couples to a transmission line in series through wire bonds to form a transmission path. Each memory die includes an on-die termination resistance circuit connected to the transmission line. The on-die termination resistance circuit provides a minimum termination resistance. The storage controller addresses a target uniform memory die of the stack of uniform memory dies for an operation. The storage controller enables the on-die termination resistance circuits of a plurality of uniform memory dies along the transmission path. The storage controller transmits a data signal for the operation to the target uniform memory die with the on-die termination resistance circuit enabled for the plurality of uniform memory dies.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: September 27, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: John Thomas Contreras, Srinivas Rajendra, Sayed Mobin, Rehan Ahmed Zakai
  • Patent number: 11302645
    Abstract: A circuit interconnect for high bandwidth and high die-count memory stacks. The circuit interconnect may include a first ground trace, a first signal trace, a second ground trace, and a second signal trace. The first ground trace may reside in a first layer of a multilayer printed circuit board. The first signal trace may be positioned adjacent to the first ground trace within the first layer. The second ground trace may reside within a second layer of the multilayer printed circuit board. The second signal trace may be positioned adjacent to the second ground trace within the second layer.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: April 12, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: John Thomas Contreras, Sayed Mobin, Daniel Oh, Rehan Ahmed Zakai
  • Publication number: 20210407565
    Abstract: The disclosed apparatuses and method provide transmission line termination. An apparatus include a stack of uniform memory dies and a storage controller. Each uniform memory die in the stack of uniform memory dies couples to a transmission line in series through wire bonds to form a transmission path. Each memory die includes an on-die termination resistance circuit connected to the transmission line. The on-die termination resistance circuit provides a minimum termination resistance. The storage controller addresses a target uniform memory die of the for an operation. The storage controller enables the on-die termination resistance circuits of a plurality of uniform memory dies along the transmission path. The storage controller transmits a data signal for the operation to the target uniform memory die with the on-die termination resistance circuit enabled for the plurality of uniform memory dies.
    Type: Application
    Filed: June 30, 2020
    Publication date: December 30, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: John Thomas Contreras, Srinivas Rajendra, Sayed Mobin, Rehan Ahmed Zakai
  • Publication number: 20210407915
    Abstract: A circuit interconnect for high bandwidth and high die-count memory stacks. The circuit interconnect may include a first ground trace, a first signal trace, a second ground trace, and a second signal trace. The first ground trace may reside in a first layer of a multilayer printed circuit board. The first signal trace may be positioned adjacent to the first ground trace within the first layer. The second ground trace may reside within a second layer of the multilayer printed circuit board. The second signal trace may be positioned adjacent to the second ground trace within the second layer.
    Type: Application
    Filed: June 30, 2020
    Publication date: December 30, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: John Thomas Contreras, Sayed Mobin, Daniel Oh, Rehan Ahmed Zakai
  • Patent number: 10643676
    Abstract: An apparatus may include a controller die and a group of dies that communicate with each other via a transmission line. The transmission line includes a first portion integrated with a printed circuit board, and a second portion that includes a plurality of wire bonds bonded to input/output pads of the group of dies. The transmission line further includes a resistor circuit connected in series with the first portion and the second portion. The resistor circuit has a resistance value that provides reduced reflection coefficients over the transmission line between the first portion and the second portion. An on-die termination resistor circuit on the controller side is removed, with the inclusion of the resistor circuit.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: May 5, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sayed Mobin, John Thomas Contreras, Pranav Balachander
  • Patent number: 10637533
    Abstract: An apparatus includes a controller die and a group of dies that communicate with each other via a transmission line. Less than all of the dies of the group includes a respective on-die termination resistance circuit coupled to the transmission line. In some embodiments, one of the dies that includes an on-die termination resistance circuit is an end die of the group. In particular embodiments, the end die is the only die of the group that includes an on-die termination resistance circuit coupled to the transmission line. Transmission frequencies or data rates may be increased without degrading signal quality by removing capacitance associated with on-die termination resistance circuits from at least one of the dies of the group.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: April 28, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: John Thomas Contreras, Sayed Mobin, David Zhang, Gokul Kumar
  • Publication number: 20200106478
    Abstract: An apparatus includes a controller die and a group of dies that communicate with each other via a transmission line. Less than all of the dies of the group includes a respective on-die termination resistance circuit coupled to the transmission line. In some embodiments, one of the dies that includes an on-die termination resistance circuit is an end die of the group. In particular embodiments, the end die is the only die of the group that includes an on-die termination resistance circuit coupled to the transmission line. Transmission frequencies or data rates may be increased without degrading signal quality by removing capacitance associated with on-die termination resistance circuits from at least one of the dies of the group.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: John Thomas Contreras, Sayed Mobin, David Zhang, Gokul Kumar
  • Publication number: 20200105318
    Abstract: An apparatus may include a controller die and a group of dies that communicate with each other via a transmission line. The transmission line includes a first portion integrated with a printed circuit board, and a second portion that includes a plurality of wire bonds bonded to input/output pads of the group of dies. The transmission line further includes a resistor circuit connected in series with the first portion and the second portion. The resistor circuit has a resistance value that provides reduced reflection coefficients over the transmission line between the first portion and the second portion. An on-die termination resistor circuit on the controller side is removed, with the inclusion of the resistor circuit.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: Sayed Mobin, John Thomas Contreras, Pranav Balachander
  • Patent number: 10461965
    Abstract: An active low-power termination circuit includes a first leg of a pair of transistors connected in series between the high supply level and ground, where the termination input is at a node between the transistors of the first node. A second leg uses a feed forward mechanism to control the voltage levels on the control gates of the transistors of the first leg. The second leg includes a second pair diode connected transistors, each of which is has its control gate connected to the control gate of the corresponding transistor in the first leg. A variable current source connected in series with the transistors of the second leg and is controlled by the output of a difference amplifier that has one input connect to an intermediate node of the second leg and a second input connected to a reference level intermediate to the high supply level and ground.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: October 29, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: John Thomas Contreras, Rehan Zakai, Sayed Mobin