Patents by Inventor Sayfe Kiasei

Sayfe Kiasei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MOS folded source-coupled logic
    Patent number: 5149992
    Abstract: In integrated circuitry having both analog and digital circuits fabricated on the same substrate, switching transients produced by the digital circuitry can propagate through the substrate and induce deleterious effects in the associated analog circuitry. Such switching transients are greatly minimized by a CMOS source-coupled current-steering differential logic topology. In the preferred embodiment, gain and level shifting functions are merged, and connections to the power bus are made through constant current sources.
    Type: Grant
    Filed: April 30, 1991
    Date of Patent: September 22, 1992
    Assignee: The State of Oregon Acting by and Through the State Board of Higher Education on Behalf of Oregon State University
    Inventors: David J. Allstot, Sayfe Kiasei