Patents by Inventor Sayok CHATTOPADHYAY

Sayok CHATTOPADHYAY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11742253
    Abstract: An integrated circuit (IC) package that is to be incorporated into a computing device may include a metallization structure with circuits and/or other elements such as capacitors or inductors thereon. Pads for input/output (I/O) (or other) purposes may also be present at different locations on the metallization structure. Exemplary aspects of the present disclosure allow mold material to be placed over the circuits and/or other elements in readily-customizable configurations so as to allow placement of the I/O pads in any desired location on the metallization structure. Specifically, before the mold material is applied to the metallization structure, a mask material such as tape may be applied to portions of the metallization structure that contain I/O pads or otherwise have reasons to not have mold material thereon. The mold material is applied, and the mask material is removed, taking unwanted mold material with the mask material.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: August 29, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Sayok Chattopadhyay, Rajneesh Kumar, Srikanth Kulkarni
  • Patent number: 11211263
    Abstract: Certain aspects of the present disclosure provide apparatus and techniques for partially molding packages for integrated circuits. A packaged assembly for integrated circuits includes: a substrate having at least one mold barrier between a first region on a first surface of the substrate and a second region on the first surface; a die attached to the substrate; one or more components attached to the substrate in the first region; and a first encapsulant over the one or more components in the first region, wherein the at least one mold barrier is configured to block a portion of the first encapsulant from moving from the first region of the substrate to the second region of the substrate during an application of the first encapsulant.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: December 28, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Srikanth Kulkarni, Rajneesh Kumar, Sayok Chattopadhyay
  • Publication number: 20210351096
    Abstract: An integrated circuit (IC) package that is to be incorporated into a computing device may include a metallization structure with circuits and/or other elements such as capacitors or inductors thereon. Pads for input/output (I/O) (or other) purposes may also be present at different locations on the metallization structure. Exemplary aspects of the present disclosure allow mold material to be placed over the circuits and/or other elements in readily-customizable configurations so as to allow placement of the I/O pads in any desired location on the metallization structure. Specifically, before the mold material is applied to the metallization structure, a mask material such as tape may be applied to portions of the metallization structure that contain I/O pads or otherwise have reasons to not have mold material thereon. The mold material is applied, and the mask material is removed, taking unwanted mold material with the mask material.
    Type: Application
    Filed: December 3, 2020
    Publication date: November 11, 2021
    Inventors: Sayok Chattopadhyay, Rajneesh Kumar, Srikanth Kulkarni
  • Publication number: 20210151330
    Abstract: Certain aspects of the present disclosure provide apparatus and techniques for partially molding packages for integrated circuits. A packaged assembly for integrated circuits includes: a substrate having at least one mold barrier between a first region on a first surface of the substrate and a second region on the first surface; a die attached to the substrate; one or more components attached to the substrate in the first region; and a first encapsulant over the one or more components in the first region, wherein the at least one mold barrier is configured to block a portion of the first encapsulant from moving from the first region of the substrate to the second region of the substrate during an application of the first encapsulant.
    Type: Application
    Filed: November 19, 2019
    Publication date: May 20, 2021
    Inventors: Srikanth KULKARNI, Rajneesh KUMAR, Sayok CHATTOPADHYAY