Abstract: A 3D CMOS image sensor is provided in the present invention, including a semiconductor substrate, a photodiode and a well formed in the semiconductor substrate, a shallow trench isolation (STI) layer formed on a front surface of the semiconductor substrate, a fin protruding upwardly from the semiconductor substrate through the STI layer, wherein the fin is composed of the photodiode and the well, a first gate spanning the photodiode portion and the well portion abutting the photodiode portion of the fin to constitute a transfer transistor, a second gate spanning in the middle of the well portion of the fin to constitute a reset transistor, and a floating diffusion region in the well portion of the fin between the first gate and the second gate electrically connecting the transfer transistor and the reset transistor.

Abstract: Provided are an image sensor and a manufacturing method thereof. In the image sensor, an insulating layer and a first silicon layer are sequentially on a silicon base. A first isolation structure is in the first silicon layer to define an active area (AA). A doped region is in a part of the first silicon layer in the AA and in a part of the silicon base thereunder. A second silicon layer is in a part of the first silicon layer in the AA and extends into the silicon base. An interconnection structure is on the first silicon layer and electrically connected with a transistor. A second isolation structure is in the silicon base under the first isolation structure and connected to the insulating layer. A passivation layer surrounds the silicon base and is connected to the doped region. A microlens is on the silicon base.

Abstract: An image sensor includes a semiconductor substrate, a photodiode formed in the semiconductor substrate, a microlens disposed over the photodiode, a first transfer transistor, a second transfer transistor and a capacitor. The first transfer transistor and the second transfer transistor are formed on the semiconductor substrate, and a memory node is formed in the semiconductor substrate between the first transfer transistor and the second transfer transistor, wherein the first transfer transistor is coupled to the photodiode. The capacitor is formed between the first transfer transistor and the second transfer transistor, and the capacitor includes a first electrode coupled to the memory node, a second electrode on the first electrode and extending to an edge of the photodiode, and a dielectric layer between the first and the second electrodes.

Abstract: An image sensor includes a semiconductor substrate, a photodiode formed in the semiconductor substrate, a microlens disposed over the photodiode, a first transfer transistor, a second transfer transistor and a capacitor. The first transfer transistor and the second transfer transistor are formed on the semiconductor substrate, and a memory node is formed in the semiconductor substrate between the first transfer transistor and the second transfer transistor, wherein the first transfer transistor is coupled to the photodiode. The capacitor is formed between the first transfer transistor and the second transfer transistor, and the capacitor includes a first electrode coupled to the memory node, a second electrode on the first electrode and extending to an edge of the photodiode, and a dielectric layer between the first and the second electrodes.

Abstract: A method of fabricating a light pipe of an image sensing device including following steps is provided. A substrate is provided. The substrate includes a pixel region and a periphery region. A light sensing region has been formed in the substrate. The light sensing region is located in the pixel region. A dielectric layer is formed on the substrate. An interconnection structure and a light-blocking metal layer have been formed in the dielectric layer. The light-blocking metal layer is located over the interconnection structure, and the light-blocking metal layer has an opening exposing the light sensing region. A portion of the dielectric layer exposed by the opening is removed by using the light-blocking metal layer as a mask to form the light pipe in the dielectric layer.

Abstract: An image sensor device includes a substrate having a first conductivity type. A plurality of photo-sensing regions including a first, a second, and a third photo-sensing regions corresponding to the R, G, B pixels are provided on the substrate. An insulation structure is disposed on the substrate to separate the photo-sensing regions from one another. A photodiode structure is formed within each photo-sensing region. A deep well structure having a second conductivity type. The deep well structure only overlaps with the second and third photo-sensing regions. The deep well structure does not overlap with the first photo-sensing region.

Abstract: A method of manufacturing a non-volatile memory is provided. An insulating layer, a conductive material layer and a polish stop layer are sequentially on a substrate. Trenches are formed in a portion of the substrate, the polish stop layer, the conductive material layer and the insulating layer, and the conductive material layer is segmented to form conductive blocks. A dielectric material layer is formed to cover the polish stop layer and fill the trenches. A chemical mechanical polishing process is performed until exposing a surface of the polish stop layer. A portion of the dielectric layer is removed to form trench isolation structures. A portion of sidewalls of each conductive block is removed to form floating gates. A width of each floating gate is decreased gradually from bottom to top.

Abstract: A method of fabricating a non-volatile memory is provided. A memory cell array having first memory units and second memory units is formed on a substrate. Then, a source region and a drain region are formed in the substrate on the respective sides of the memory cell array. Next, a patterned first inter-layer insulating layer is formed on the substrate to form a first trench and a number of second trenches. A conductive layer is formed on the substrate to form a source line in the first trench and conductive lines in the second trenches. A second inter-layer insulating layer is formed on the substrate and then a conductive plug having contact with the drain region is formed in the second inter-layer insulating layer and the first inter-layer insulating layer. Then, a bit line having contact with the conductive plug is formed on the second inter-layer insulating layer.

Abstract: A non-volatile memory having a plurality of memory units each including a select unit and a memory unit is provided. The select unit is disposed on the substrate. The memory cell is disposed on one sidewall of the select unit and the substrate. The select unit includes a gate disposed on the substrate and a first gate dielectric layer disposed between the gate and the substrate. The memory cell includes a pair of floating gate disposed on the substrate, a control gate disposed on the upper surface of the floating gates, an inter-gate dielectric layer disposed between the floating gate and the control gate, a tunneling dielectric layer disposed between the floating gate and the substrate and a second gate dielectric layer disposed between the bottom of the control gate and the substrate.

Abstract: A method of fabricating non-volatile memory is provided. A plurality of first memory cells is formed on the memory cell region of a substrate. Each first memory cell comprises a first composite layer, a first gate and a cap layer. There is a gap between two adjacent first memory cells. Then, a plurality of gates is formed in the respective gaps. The gates together with a second composite layer form a plurality of second memory cells. The second memory cells and the first memory cells together constitute a memory cell column. In the meantime, a plurality of gate structures is also formed on the peripheral circuit region. The gates in the gaps and the gates in the peripheral circuit region are fabricated using different conductive layers.

Abstract: A flash memory cell including a first conductive type substrate, a second conductive type well, a patterned film layer, a second conductive type doped region, a tunneling dielectric layer, a plurality of floating gates, an inter-gate dielectric layer and a plurality of control gates is provided. The floating gates are formed on the first conductive type substrate outside the patterned film layer. The floating gates have a thickness greater than the patterned film layer. Thus, the overlapping area between the floating gates and the control gates and hence the coupling ratio of the flash memory cell is increased.

Abstract: A method of fabricating a non-volatile memory is provided. A memory cell array having first memory units and second memory units is formed on a substrate. Then, a source region and a drain region are formed in the substrate on the respective sides of the memory cell array. Next, a patterned first inter-layer insulating layer is formed on the substrate to form a first trench and a plurality of second trenches. A conductive layer is formed on the substrate to form a source line in the first trench and conductive lines in the second trenches. A second inter-layer insulating layer is formed on the substrate and then a conductive plug having contact with the drain region is formed in the second inter-layer insulating layer and the first inter-layer insulating layer. Then, a bit line having contact with the conductive plug is formed on the second inter-layer insulating layer.

Abstract: A non-volatile memory having a plurality of memory units is provided. Each memory unit includes a first memory cell and a second memory cell. The first memory cell is disposed on the substrate. The second memory cell is disposed on one sidewall of the first memory cell and the substrate. The first memory cell includes a first control gate disposed on the substrate and a composite layer disposed between the first control gate and the substrate. The second memory cell includes a pair of floating gates disposed on the substrate, a second control gate disposed on the upper surface of the two floating gates, an inter-gate dielectric layer disposed between the floating gate and the second control gate, a tunneling dielectric layer disposed between the floating gate and the substrate and a gate dielectric layer disposed between the bottom of the second control gate and the substrate.

Abstract: A non-volatile memory having a plurality of memory units is provided. Each memory unit includes a first memory cell and a second memory cell. The first memory cell is disposed on the substrate. The second memory cell is disposed on one sidewall of the first memory cell and the substrate. The first memory cell includes a first control gate disposed on the substrate and a composite layer disposed between the first control gate and the substrate. The second memory cell includes a pair of floating gates disposed on the substrate, a second control gate disposed on the upper surface of the two floating gates, an inter-gate dielectric layer disposed between the floating gate and the second control gate, a tunneling dielectric layer disposed between the floating gate and the substrate and a gate dielectric layer disposed between the bottom of the second control gate and the substrate.

Abstract: A non-volatile memory having a memory cell formed on a substrate is provided. A trench is formed in the substrate. The memory cell has a first gate, a second gate, a charge storage layer, a first source/drain region and a second source/drain region. The first gate is disposed in the trench of the substrate. The second gate is disposed on the substrate at one side of the trench. The charge storage layer is disposed between the first gate and the substrate and between the second gate and the substrate. The first source/drain region is disposed in the substrate at the bottom of the trench. The second source/drain region is disposed in the substrate at one side of the second gate.

Abstract: A method of fabricating non-volatile memory is provided. A plurality of first memory cells is formed on the memory cell region of a substrate. Each first memory cell includes a first composite layer, a first gate and a cap layer. There is a gap between two adjacent first memory cells. Then, a plurality of gates is formed in the respective gaps. The gates together with a second composite layer form a plurality of second memory cells. The second memory cells and the first memory cells together constitute a memory cell column. In the meantime, a plurality of gate structures is also formed on the peripheral circuit region. The gates in the gaps and the gates in the peripheral circuit region are formed using the same conductive layers.

Abstract: A method of fabricating a non-volatile memory is described. A plurality of first memory units having gaps between each other is formed over a substrate. Insulating spacers are formed on the sidewalls of the first memory units. A composite layer is formed on the substrate and the gaps between the first memory units are filled with a doped polysilicon layer. Thereafter, a portion of the doped polysilicon layer is removed to form trenches. After that, a metallic layer fills the trenches. A portion of the metallic layer is removed to form a plurality of gates. The gates and the composite layer together form a plurality of second memory units. The second memory units and the first memory units together constitute a memory cell column. Then, a source region and a drain region are formed in the substrate adjacent to the two sides of the memory cell column.

Abstract: A method for manufacturing semiconductor device is provided. First, a substrate is provided. Then, a plurality of first gate lines disposed in parallel to each other and a first dummy gate line disposed in a direction perpendicular to the first gate lines are formed on the substrate. There is a first gap between the first dummy gate line and the first gate lines and there is a second gap between every pair of adjacent first gate lines. Thereafter, a second composite layer and a conductive layer are sequentially formed over the substrate. The conductive layer is etched back to form a plurality of second device structures that completely fills the second gaps. Then, the conductive layer in the first gap is removed.

Abstract: A non-volatile memory having a plurality of gate structures, a plurality of charge storage layers and two doped regions is provided. The gate structures are disposed on the substrate and connected in series. The charge storage layers are disposed between every two neighboring gate structures respectively. The gate structures and the charge storage layers form a memory cell column. The two doped regions are disposed in the substrate at both sides of the memory cell column.

Abstract: A non-volatile memory is provided. At least two bit lines are disposed in a substrate. The two bit lines are arranged in parallel and extend in a first direction. A plurality of select gate structures is disposed on the substrate between the two bit lines respectively. The select gate structures are arranged in parallel and extend in a first direction. A gap is disposed between each two neighboring select gate structures. A plurality of control gate lines is disposed on the substrate and fills in the gaps between two neighboring select gate structures respectively. The control gate lines are arranged in parallel and extend in a second direction, which crosses the first direction. A plurality of charge storage layers is disposed between the select gate structures and control gate lines respectively.