Abstract: An apparatus for injecting solder material in via holes located in a top surface of a wafer is provided. The apparatus includes an injection head having a contact surface for contacting the top surface of the wafer, and at least one aperture for injecting the solder material though the injection head into the via holes. The apparatus further includes an evacuating device connected to the injection head for evacuating gas from the via holes. The injection head has a chamfer part on an edge of a contact surface contacting the top surface of the wafer.

Abstract: There is provided a circuit module where a sufficient amount of underfill resin may be supplied to corner portions of a semiconductor chip. A circuit module includes a circuit board provided with a plurality of electrode pads on a surface of the board, a semiconductor chip arranged on the board, the chip including a surface and a back surface, where each of a plurality of solder bumps and provided on the back surface is solder joined to a corresponding one of the plurality of electrode pads, and an underfill provided between the surface of the board and the back surface of the chip. Furthermore, the chip includes an eaves portion of a predetermined thickness at an outer periphery of the surface, and the underfill forms a fillet extending from a bottom surface of the eaves portion to the surface of the board along a side wall of the chip.

Abstract: A via structure for electric connection is disclosed. The via structure includes a substrate that has a first surface and a via hole opened to the first surface. The via structure includes also a stress buffer layer disposed on the first surface of the substrate, which has an opening aligned to the via hole of the substrate. The via structure further includes a conductive body formed in the via hole of the substrate at least up to the level of the first surface of the substrate. In the via structure, the stress buffer layer receives the conductive body extending into the opening over the level of the first surface of the substrate and/or covers, at least in part, the edge of the first surface around the via hole of the substrate.

Abstract: An organic substrate includes a core layer including organic materials; a first buildup layer on a top surface of the core layer; a second buildup layer on a bottom surface of the core layer; and at least one correction layer formed on at least one part of surfaces of the first buildup layer and the second buildup layer, wherein the correction layer has a thickness which has been calculated using properties of constituent materials including the coefficient of thermal expansion (CTE) and the Young's modulus of the core layer, and CTEs and the Young's modulus of the first and the second buildup layers for reducing warpage of the organic substrate.

Abstract: Methods for fabricating a via structure are disclosed. In one method, fabricating the via structure includes disposing a stress buffer layer on a first surface of a substrate. The stress buffer layer has an opening aligned to a via hole of the substrate. The method further includes filling the via hole with a conductive material at least up to the first surface of the substrate. The stress buffer layer reduces stress generated due to coefficient of thermal expansion mismatch associated with the via hole and the substrate, and the conductive material extends into the opening over the level of the first surface of the substrate and/or covers, at least in part, the edge of the first surface of the substrate around the via hole.

Abstract: A via structure for electric connection is disclosed. The via structure includes a substrate that has a first surface and a via hole opened to the first surface. The via structure includes also a stress buffer layer disposed on the first surface of the substrate, which has an opening aligned to the via hole of the substrate. The via structure further includes a conductive body formed in the via hole of the substrate at least up to the level of the first surface of the substrate. In the via structure, the stress buffer layer receives the conductive body extending into the opening over the level of the first surface of the substrate and/or covers, at least in part, the edge of the first surface around the via hole of the substrate.

Abstract: An organic substrate includes a core layer including organic materials; a first buildup layer on a top surface of the core layer; a second buildup layer on a bottom surface of the core layer; and at least one correction layer formed on at least one part of surfaces of the first buildup layer and the second buildup layer, wherein the correction layer has a thickness which has been calculated using properties of constituent materials including the coefficient of thermal expansion (CTE) and the Young's modulus of the core layer, and CTEs and the Young's modulus of the first and the second buildup layers for reducing warpage of the organic substrate.

Abstract: There is provided a circuit module where a sufficient amount of underfill resin may be supplied to corner portions of a semiconductor chip. A circuit module includes a circuit board provided with a plurality of electrode pads on a surface of the board, a semiconductor chip arranged on the board, the chip including a surface and a back surface, where each of a plurality of solder bumps and provided on the back surface is solder joined to a corresponding one of the plurality of electrode pads, and an underfill provided between the surface of the board and the back surface of the chip. Furthermore, the chip includes an eaves portion of a predetermined thickness at an outer periphery of the surface, and the underfill forms a fillet extending from a bottom surface of the eaves portion to the surface of the board along a side wall of the chip.

Abstract: A via structure for electric connection is disclosed. The via structure includes a substrate that has a first surface and a via hole opened to the first surface. The via structure includes also a stress buffer layer disposed on the first surface of the substrate, which has an opening aligned to the via hole of the substrate. The via structure further includes a conductive body formed in the via hole of the substrate at least up to the level of the first surface of the substrate. In the via structure, the stress buffer layer receives the conductive body extending into the opening over the level of the first surface of the substrate and/or covers, at least in part, the edge of the first surface around the via hole of the substrate.

Abstract: A via structure for electric connection is disclosed. The via structure includes a substrate that has a first surface and a via hole opened to the first surface. The via structure includes also a stress buffer layer disposed on the first surface of the substrate, which has an opening aligned to the via hole of the substrate. The via structure further includes a conductive body formed in the via hole of the substrate at least up to the level of the first surface of the substrate. In the via structure, the stress buffer layer receives the conductive body extending into the opening over the level of the first surface of the substrate and/or covers, at least in part, the edge of the first surface around the via hole of the substrate.

Abstract: There is provided a circuit module where a sufficient amount of underfill resin may be supplied to corner portions of a semiconductor chip. A circuit module includes a circuit board provided with a plurality of electrode pads on a surface of the board, a semiconductor chip arranged on the board, the chip including a surface and a back surface, where each of a plurality of solder bumps and provided on the back surface is solder joined to a corresponding one of the plurality of electrode pads, and an underfill provided between the surface of the board and the back surface of the chip. Furthermore, the chip includes an eaves portion of a predetermined thickness at an outer periphery of the surface, and the underfill forms a fillet extending from a bottom surface of the eaves portion to the surface of the board along a side wall of the chip.

Abstract: A method for reducing warpage on an organic substrate. The method includes: preparing an organic substrate, which includes (i) a core layer having an organic material, (ii) a first buildup layer on a front surface of the core layer, and (iii) a second buildup layer on a back surface of the core layer, measuring warpage of the organic substrate, calculating a thickness of a correction layer for reducing the warpage using properties of constituent materials including the coefficient of thermal expansion (CTE) and the Young's modulus of the core layer, and CTEs and the Young's modulus of the first and the second buildup layers, and forming at least one correction layer having the thickness on at least one part of surfaces of the first buildup layer and the second buildup layer. A system and an organic substrate is also provided.

Abstract: A method that minimizes adjustment of a wiring layer in reducing a warpage of a multilayered substrate and enables location of a part of a wiring layer that needs correction in order to reduce the warpage. The difference in average coefficient of thermal expansion, ??, varies in a substrate. The method focuses in on the difference in ?? with a great length scale (low frequency) having a relatively significant effect on the warpage compared to the difference in ?? with a smaller length scale (high frequency) and corrects only the difference in ?? with a greater length scale. The distribution of the difference in ?? in a plane of substrate is determined. Then digital filtering is performed to extract only the difference in ?? with a low frequency and the difference in ?? between before and after correction, thereby revealing a part that requires correction.

Abstract: A method for reducing warpage on an organic substrate. The method includes: preparing an organic substrate, which includes (i) a core layer having an organic material, (ii) a first buildup layer on a front surface of the core layer, and (iii) a second buildup layer on a back surface of the core layer, measuring warpage of the organic substrate, calculating a thickness of a correction layer for reducing the warpage using properties of constituent materials including the coefficient of thermal expansion (CTE) and the Young's modulus of the core layer, and CTEs and the Young's modulus of the first and the second buildup layers, and forming at least one correction layer having the thickness on at least one part of surfaces of the first buildup layer and the second buildup layer. A system and an organic substrate is also provided.

Abstract: The present invention includes the following steps: setting the thickness of an interposer to an initial value; determining the axial force of the interposer and the radius of curvature of the warpage caused by the difference in the thermal expansion coefficients of the supporting substrate, the joined layer and the interposer at the set thickness; determining the absolute value of the stress on the chip-connecting surface of the interposer from the stress due to the axial force of the interposer and the stress due to the warpage using the determined axial force and the radius of curvature; determining whether or not the absolute value of the stress is within a tolerance; changing the thickness of the interposer by a predetermined value; and confirming the set thickness as the thickness of the interposer when the determined absolute value of the stress is within the tolerance.

Abstract: A method that minimizes adjustment of a wiring layer in reducing a warpage of a multilayered substrate and enables location of a part of a wiring layer that needs correction in order to reduce the warpage. The difference in average coefficient of thermal expansion, ??, varies in a substrate. The method focuses in on the difference in ?? with a great length scale (low frequency) having a relatively significant effect on the warpage compared to the difference in ?? with a smaller length scale (high frequency) and corrects only the difference in ?? with a greater length scale. The distribution of the difference in ?? in a plane of substrate is determined. Then digital filtering is performed to extract only the difference in ?? with a low frequency and the difference in ?? between before and after correction, thereby revealing a part that requires correction.

Abstract: A method that minimizes adjustment of a wiring layer in reducing a warpage of a multilayered substrate and enables location of a part of a wiring layer that needs correction in order to reduce the warpage. The difference in average coefficient of thermal expansion, ??, varies in a substrate. The method focuses in on the difference in ?? with a great length scale (low frequency) having a relatively significant effect on the warpage compared to the difference in ?? with a smaller length scale (high frequency) and corrects only the difference in ?? with a greater length scale. The distribution of the difference in ?? in a plane of substrate is determined. Then digital filtering is performed to extract only the difference in ?? with a low frequency and the difference in ?? between before and after correction, thereby revealing a part that requires correction.

Abstract: There is provided a circuit module where a sufficient amount of underfill resin may be supplied to corner portions of a semiconductor chip. A circuit module includes a circuit board provided with a plurality of electrode pads on a surface of the board, a semiconductor chip arranged on the board, the chip including a surface and a back surface, where each of a plurality of solder bumps and provided on the back surface is solder joined to a corresponding one of the plurality of electrode pads, and an underfill provided between the surface of the board and the back surface of the chip. Furthermore, the chip includes an eaves portion of a predetermined thickness at an outer periphery of the surface, and the underfill forms a fillet extending from a bottom surface of the eaves portion to the surface of the board along a side wall of the chip.

Abstract: [Problem] To reduce thermal resistance between a heating body and a radiating body. [Solving Means] Provided is a sheet having a high thermal conductivity and flexibility, in which graphite layers and elastic layers are stacked alternately, and each of ends of the graphite layer in its surface direction or each of ends of a graphene protrudes from an end of the elastic layer and bends so as to cover at least a part of the end of the elastic layer. By placing a sheet of the present invention in a space (gap) between a heating body and a radiating body, thermal resistance at the gap, especially contact thermal resistance on a joint surface, can be reduced even in the case where flatness of a surface of the heating body or a surface of the radiating body is small.

Abstract: A method that minimizes adjustment of a wiring layer in reducing a warpage of a multilayered substrate and enables location of a part of a wiring layer that needs correction in order to reduce the warpage. The difference in average coefficient of thermal expansion, ??, varies in a substrate. The method focuses in on the difference in ?? with a great length scale (low frequency) having a relatively significant effect on the warpage compared to the difference in ?? with a smaller length scale (high frequency) and corrects only the difference in ?? with a greater length scale. The distribution of the difference in ?? in a plane of substrate is determined. Then digital filtering is performed to extract only the difference in ?? with a low frequency and the difference in ?? between before and after correction, thereby revealing a part that requires correction.