Patents by Inventor Scot Graham

Scot Graham has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070263470
    Abstract: Techniques for reducing gate induced drain leakage (GIDL) in memory devices utilizing negative wordline architectures. More specifically, a method and apparatus are provided to determine whether any of the word lines in a section of a memory array are active. If any one of the plurality of word lines is active, each of the inactive word lines in the section are coupled to a negative voltage level. If none of the plurality of word lines is active, each of the plurality of word lines is coupled to ground to reduce GIDL.
    Type: Application
    Filed: July 17, 2007
    Publication date: November 15, 2007
    Inventors: Scott Derner, Venkatraghavan Bringivijayaraghavan, Abhay Dixit, Scot Graham, Stephen Porter, Ethan Williford
  • Publication number: 20060256630
    Abstract: A method and apparatus is provided for reducing the current in a memory device. Peripheral device control signals are translated to the wordline off voltage level, such as a negative wordline voltage. The translated signals prevent the peripheral devices from conducting current in the wordline off mode, even if a wordline-to-digitline short should occur. The control signals may include a column select signal for a column select device and an active pull-up signal for a sense amplifier, among others. Additionally, an equalization circuit having high and low resistance components is provided for the memory device. The equalization circuit limits current, even if a wordline-to-digitline short occurs.
    Type: Application
    Filed: July 19, 2006
    Publication date: November 16, 2006
    Inventors: Scott Derner, Stephen Porter, Scot Graham, Ethan Williford, Kevin Duesman
  • Publication number: 20060139988
    Abstract: A memory device includes isolation devices located between-memory cells. A plurality of isolation lines connects the isolation devices to a positive voltage during normal operations but still keeps the isolation devices in the off state to provide isolation between the memory cells. A current control circuit is placed between the isolation lines and a power node for reducing a current flowing between the isolation lines and the power node in case a deflect occurs at any one of isolation devices.
    Type: Application
    Filed: February 21, 2006
    Publication date: June 29, 2006
    Inventors: Luan Tran, Stephen Porter, Scot Graham, Steven Howell
  • Publication number: 20060023493
    Abstract: A method and apparatus is provided for reducing the current in a memory device. Peripheral device control signals are translated to the wordline off voltage level, such as a negative wordline voltage. The translated signals prevent the peripheral devices from conducting current in the wordline off mode, even if a wordline-to-digitline short should occur. The control signals may include a column select signal for a column select device and an active pull-up signal for a sense amplifier, among others. Additionally, an equalization circuit having high and low resistance components is provided for the memory device. The equalization circuit limits current, even if a wordline-to-digitline short occurs.
    Type: Application
    Filed: July 29, 2004
    Publication date: February 2, 2006
    Inventors: Scott Derner, Stephen Porter, Scot Graham, Ethan Williford, Kevin Duesman
  • Publication number: 20060023542
    Abstract: Techniques for reducing gate induced drain leakage (GIDL) in memory devices utilizing negative wordline architectures. More specifically, a method and apparatus are provided to determine whether any of the word lines in a section of a memory array are active. If any one of the plurality of word lines is active, each of the inactive word lines in the section are coupled to a negative voltage level. If none of the plurality of word lines is active, each of the plurality of word lines is coupled to ground to reduce GIDL.
    Type: Application
    Filed: July 27, 2004
    Publication date: February 2, 2006
    Inventors: Scott Derner, Venkatraghavan Bringivijayaraghavan, Abhay Dixit, Scot Graham, Stephen Porter, Ethan Williford
  • Publication number: 20050099836
    Abstract: A memory device includes isolation devices located between memory cells. A plurality of isolation lines connects the isolation devices to a positive voltage during normal operations but still keeps the isolation devices in the off state to provide isolation between the memory cells. A current control circuit is placed between the isolation lines and a power node for reducing a current flowing between the isolation lines and the power node in case a deflect occurs at any one of isolation devices.
    Type: Application
    Filed: November 29, 2004
    Publication date: May 12, 2005
    Inventors: Luan Tran, Stephen Porter, Scot Graham, Steven Howell
  • Patent number: 5031062
    Abstract: A method for assembling disks in a disk drive apparatus is disclosed, as well as the resultant assembly. The method reduces the occurrence of disk head crashes resulting from penetration of the air bearing on which the disk head rides because of one or more surface irregularities found in the disk surface at or near inner diameter portions of the disk which lead to rippling of the disk surface. The elimination or reduction in size of the surface irregularities is achieved using a flowable filler material that is received by the surface irregularities and remains therein after the disk or disks are clamped to a spindle. The filler material is preferably an adhesive and it reduces any differences in the surface topography of the disk and the accompanying clamping-related parts. Bowing of the disk at its inner diameter portions due to uneven clamping forces is also reduced in the present invention.
    Type: Grant
    Filed: January 18, 1991
    Date of Patent: July 9, 1991
    Assignee: PrairieTek Corporation
    Inventors: Joseph A. Wood, Dennis Ogden, Scot Graham