Abstract: Embodiments of the invention are directed to an integrated circuit (IC) structure that includes a memory element a non-sacrificial hardmask stack over the memory element. The non-sacrificial hardmask stack includes a first hardmask region and a second hardmask region. A compressive stress level of the first hardmask region is greater than a compressive stress level of the second hardmask region.

Abstract: A wire interconnect, a wire interconnect structure, and a method to form wire interconnect structures with locally widened profiles. The wire interconnect may include a first portion of the wire interconnect with a first width. The wire interconnect may also include a second portion of the wire interconnect with a second width, where the second width is greater than the first width, and where the second portion of the wire interconnect is above the first portion of the wire interconnect. The wire interconnect may also include a third portion of the wire interconnect with a third width, where the third width is less than the second width, and where the third portion of the wire interconnect is above the second portion of the wire interconnect.

Abstract: A memory device includes a magnetic tunnel junction pillar above a bottom electrode. A sidewall spacer is disposed along sidewalls of the magnetic tunnel junction pillar with an uppermost surface of the sidewall spacer being coplanar with an uppermost surface of the magnetic tunnel junction pillar. A dielectric hardmask composed of an amorphous dielectric material is disposed above a first portion of the uppermost surface of the magnetic tunnel junction pillar, the dielectric hardmask includes a hemispherical shape. A top electrode is located surrounding the dielectric hardmask and above the uppermost surface of the sidewall spacer and a second portion of the uppermost surface of the magnetic tunnel junction pillar extending outwards from the dielectric hardmask.

Abstract: Methods of manufacturing logic or memory devices are provided. The method comprises pre-cleaning a surface of a transistor device, the transistor device comprising a first source/drain material and a second source/drain material; exposing the surface of the transistor device to a growth inhibitor; selectively depositing a silicon-containing mask layer source/drain material; and densifying the silicon-containing mask layer. The processing method is performed in a processing tool without breaking vacuum.

Abstract: Methods of manufacturing electronic devices, e.g., logic devices or memory devices, are provided. The method comprises pre-cleaning a top surface of a film stack, the film stack comprising alternating layers of a first material layer and a second material layer and having one or more of a memory hole and a slit pattern opening extending through the film stack; pre-treating the top surface of the film stack to form a treated surface; exposing the treated surface to a growth inhibitor; selectively depositing a silicon-containing dielectric layer in a region of the film stack; and densifying the silicon-containing dielectric layer. The processing method is performed in a processing tool without breaking vacuum.

Abstract: A chip is manufactured using a method for forming a back-end-of-line (BEOL) layer on an IC chip surface comprises providing a first layer on top of a substrate layer of the IC chip, the first layer comprising a bottom portion of a metallic fill region having a first width as seen in a vertical cross-section of the IC chip. The method further provides a second layer on top of the first layer. The second layer comprises a middle portion of the metallic fill region having a second width that is wider than the bottom portion of the metallic fill region. The method provides a third layer on top of the second layer. The third layer comprises a top portion of the metallic fill region having a third width as seen in the vertical cross-section of the IC chip that is narrower than the middle portion of the metallic fill region.

Abstract: A wire interconnect, a wire interconnect structure, and a method to form wire interconnect structures with locally widened profiles. The wire interconnect may include a first portion of the wire interconnect with a first width. The wire interconnect may also include a second portion of the wire interconnect with a second width, where the second width is greater than the first width, and where the second portion of the wire interconnect is above the first portion of the wire interconnect. The wire interconnect may also include a third portion of the wire interconnect with a third width, where the third width is less than the second width, and where the third portion of the wire interconnect is above the second portion of the wire interconnect.

Abstract: A memory device includes a magnetic tunnel junction pillar above a bottom electrode. A sidewall spacer is disposed along sidewalls of the magnetic tunnel junction pillar with an uppermost surface of the sidewall spacer being coplanar with an uppermost surface of the magnetic tunnel junction pillar. A dielectric hardmask composed of an amorphous dielectric material is disposed above a first portion of the uppermost surface of the magnetic tunnel junction pillar, the dielectric hardmask includes a hemispherical shape. A top electrode is located surrounding the dielectric hardmask and above the uppermost surface of the sidewall spacer and a second portion of the uppermost surface of the magnetic tunnel junction pillar extending outwards from the dielectric hardmask.

Abstract: Embodiments of the invention are directed to an integrated circuit (IC) structure that includes a memory element a non-sacrificial hardmask stack over the memory element. The non-sacrificial hardmask stack includes a first hardmask region and a second hardmask region. A compressive stress level of the first hardmask region is greater than a compressive stress level of the second hardmask region.

Abstract: An interconnect structure, and a method for forming the same includes forming recess within a dielectric layer and conformally depositing a barrier layer within the recess. A cobalt-infused ruthenium liner is formed above the barrier layer, the cobalt containing ruthenium liner formed by stacking a second liner above a first liner, the first liner positioned above the barrier layer. The first liner includes ruthenium while the second liner includes cobalt. Cobalt atoms migrate from the second liner to the first liner forming the cobalt-infused ruthenium liner. A conductive material is deposited above the cobalt-infused ruthenium liner to fill the recess followed by a capping layer made of cobalt.

Abstract: An interconnect structure, and a method for forming the same includes forming recess within a dielectric layer and conformally depositing a barrier layer within the recess. A cobalt-infused ruthenium liner is formed above the barrier layer, the cobalt containing ruthenium liner formed by stacking a second liner above a first liner, the first liner positioned above the barrier layer. The first liner includes ruthenium while the second liner includes cobalt. Cobalt atoms migrate from the second liner to the first liner forming the cobalt-infused ruthenium liner. A conductive material is deposited above the cobalt-infused ruthenium liner to fill the recess followed by a capping layer made of cobalt.