Patents by Inventor Scott A. Erjavic

Scott A. Erjavic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus and method for testing the calibration of electronic package lead inspection system
    Patent number: 5489843
    Abstract: A verification unit resembling certain aspects of an electronic package is used for testing the proper calibration of lead inspection systems. Comparison of readings provided by the system when the unit is inspected to actual values will indicate whether the system is properly calibrated.
    Type: Grant
    Filed: July 23, 1991
    Date of Patent: February 6, 1996
    Assignee: VLSI Technology, Inc.
    Inventors: Scott A. Erjavic, Lawrence E. Spanton
  • Apparatus and method for testing the calibration of a variety of electronic package lead inspection systems
    Patent number: 5477138
    Abstract: A universal verification unit resembling certain aspects of an electronic package is used for testing the proper calibration of different lead inspection systems. Comparison of readings provided by the system when the unit is inspected to actual values will indicate whether the system is properly calibrated.
    Type: Grant
    Filed: February 5, 1993
    Date of Patent: December 19, 1995
    Assignee: VLSI Technology, Inc.
    Inventors: Scott A. Erjavic, Steven H. C. Hsieh
  • System for controlling an integrated product process for semiconductor wafers and packages
    Patent number: 5355320
    Abstract: A distributed control system for controlling an integrated production process for semiconductor wafers and packages. A workstation is connected to a tester and a sorter/handler for configuring and controlling both devices. An operator need not be aware of different syntaxes and configurations required by different brands of testers, sorters/probers or handlers. The workstation is connected to a computer-aided manufacturing node to obtain setup and other processing control information and to send updated control information to the node through a network. If the data collected from the testers indicates low yield, the computer-aided manufacturing node is alerted.
    Type: Grant
    Filed: March 6, 1992
    Date of Patent: October 11, 1994
    Assignee: VLSI Technology, Inc.
    Inventors: Scott A. Erjavic, Ronald E. Frye, Jr.