Patents by Inventor Scott A. Estes

Scott A. Estes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170114382
    Abstract: Aspects of the present disclosure provide compositions and methods for increasing protein production in mammalian cells, e.g. methods of increasing mammalian cell expression of a protein of interest, comprising culturing mammalian cells that overexpress a protein of interest and are modified to overexpress a gene encoding Rab 11 or Yap1, as well as mammalian cells that overexpress a protein of interest and which are modified to overexpress a gene encoding Rab 11 or Yap1.
    Type: Application
    Filed: January 30, 2015
    Publication date: April 27, 2017
    Applicant: Biogen MA Inc.
    Inventors: John Follit, Scott Estes
  • Patent number: 7855130
    Abstract: An improved method of dicing a semiconductor wafer which substantially reduces or eliminates corrosion of copper-containing, aluminum bonding pads. The method involves continuously contacting the bonding pads with deionized water and an effective amount of a copper corrosion inhibiting agent, most preferably benzotriazole. Also disclosed, is an improved apparatus for dicing a wafer, in which a copper corrosion inhibiting agent is included in the cooling system for cooling the dicing blade.
    Type: Grant
    Filed: April 21, 2003
    Date of Patent: December 21, 2010
    Assignee: International Business Machines Corporation
    Inventors: Robert R Cadieux, Scott A Estes, Timothy C Krywanczyk
  • Publication number: 20090239235
    Abstract: Methods are disclosed to identify, select and produce a clonal population of recombinant eukaryotic host cells that stably and highly express a polypeptide of interest. Also disclosed herein are products produced by the disclosed methods and assemblies of components useful to conduct the methods.
    Type: Application
    Filed: September 18, 2007
    Publication date: September 24, 2009
    Inventors: Christine DeMaria, Scott Estes, Kenneth P. Karey, Victor Cairns
  • Publication number: 20080066864
    Abstract: An etch apparatus. The etch apparatus includes a tank coupled to a recirculating path that includes a dissolver. The dissolver includes a porous carbon matrix filter coated with silicon nitride. An etchant from the tank circulates through the recirculating path and performs a selective etching of a structure in the tank in contact with the etchant. The structure includes silicon nitride on a pad layer that includes silicon dioxide. The selective etching is characterized by the silicon nitride on the pad layer being selectively etched by the etchant relative to an etching by the etchant of the silicon dioxide. The etch apparatus further includes: means for dissolving the silicon nitride coated on the filter into the etchant at a controlled dissolution rate sufficient to cause the selective etching; and means for coating the silicon nitride onto the filter to facilitate the selective etching.
    Type: Application
    Filed: November 28, 2007
    Publication date: March 20, 2008
    Inventors: Arne Ballantine, Scott Estes, Emily Fisch, Gary Milo, Ronald Warren
  • Patent number: 7332054
    Abstract: In a process using a hot phosphoric acid etchant (12) to etch silicon nitride on a semiconductor wafer (15) submerged in a tank (11) of the etchant (12), a recirculating path is established for the etchant (12). A porous filter (35) is coated with silicon nitride and installed in the recirculating path. As the etchant (12) in the recirculating path flows through the porous filter (35), the silicon nitride on the porous filter (35) dissolves into the etchant (12). In the tank (11), the silicon nitride dissolved in the etchant (12) significantly suppresses the etch of silicon dioxide on the semiconductor wafer (15), thereby enhancing the etch selectivity of the process. Monitoring and maintaining the concentration of the silicon nitride in the etchant (12) stabilizes the etch selectivity of the process.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: February 19, 2008
    Assignee: International Business Machines Corporation
    Inventors: Arne W. Ballantine, Scott A. Estes, Emily E. Fisch, Gary Milo, Ronald A. Warren
  • Publication number: 20050026252
    Abstract: The invention relates to isolation of novel ?-actin and ribosomal protein S21 (rpS21) promoters and uses thereof. In particular, this invention features nucleotide sequences for rodent ?-actin promoters including, hamster, rat, and mouse, and hamster rpS21 promoter.
    Type: Application
    Filed: June 24, 2004
    Publication date: February 3, 2005
    Inventors: Scott Estes, Weiqun Zhang
  • Publication number: 20040209443
    Abstract: An improved method of dicing a semiconductor wafer which substantially reduces or eliminates corrosion of copper-containing, aluminum bonding pads. The method involves continuously contacting the bonding pads with deionized water and an effective amount of a copper corrosion inhibiting agent, most preferably benzotriazole. Also disclosed, is an improved apparatus for dicing a wafer, in which a copper corrosion inhibiting agent is included in the cooling system for cooling the dicing blade.
    Type: Application
    Filed: April 21, 2003
    Publication date: October 21, 2004
    Applicant: International Business Machines Corporation
    Inventors: Robert R. Cadieux, Scott A. Estes, Timothy C. Krywanczyk
  • Publication number: 20040144750
    Abstract: In a process using a hot phosphoric acid etchant (12) to etch silicon nitride on a semiconductor wafer (15) submerged in a tank (11) of the etchant (12), a recirculating path is established for the etchant (12). A porous filter (35) is coated with silicon nitride and installed in the recirculating path. As the etchant (12) in the recirculating path flows through the porous filter (35), the silicon nitride on the porous filter (35) dissolves into the etchant (12). In the tank (11), the silicon nitride dissolved in the etchant (12) significantly suppresses the etch of silicon dioxide on the semiconductor wafer (15), thereby enhancing the etch selectivity of the process. Monitoring and maintaining the concentration of the silicon nitride in the etchant (12) stabilizes the etch selectivity of the process.
    Type: Application
    Filed: January 20, 2004
    Publication date: July 29, 2004
    Inventors: Arne W. Ballantine, Scott A. Estes, Emily E. Fisch, Gary Milo, Ronald A. Warren
  • Patent number: 6758912
    Abstract: A method for forming for inhibiting the buildup of cerlum-containing deposits in a process tool is disclosed. The method involves spraying a solution of a dilute acid, preferably nitric or perchloric acid, through the chamber and bowl rinse nozzles of the process tool. The method is less time consuming than previous methods for inhibiting the buildup of cerium-containing deposits and can be conveniently carried out at the end of every shift.
    Type: Grant
    Filed: October 29, 2002
    Date of Patent: July 6, 2004
    Assignee: International Business Machines Corporation
    Inventors: Virginia Chi-Chuen Chao, Scott A. Estes, Thomas B. Faure, Thomas M. Wagner
  • Patent number: 6699400
    Abstract: In a process using a hot phosphoric acid etchant (12) to etch silicon nitride on a semiconductor wafer (15) submerged in a tank (11) of the etchant (12), a recirculating path is established for the etchant (12). A porous filter (35) is coated with silicon nitride and installed in the recirculating path. As the etchant (12) in the recirculating path flows through the porous filter (35), the silicon nitride on the porous filter (35) dissolves into the etchant (12). In the tank (11), the silicon nitride dissolved in the etchant (12) significantly suppresses the etch of silicon dioxide on the semiconductor wafer (15), thereby enhancing the etch selectivity of the process. Monitoring and maintaining the concentration of the silicon nitride in the etchant (12) stabilizes the etch selectivity of the process.
    Type: Grant
    Filed: June 4, 1999
    Date of Patent: March 2, 2004
    Inventors: Arne W. Ballantine, Scott A. Estes, Emily E. Fisch, Gary Milo, Ronald A. Warren
  • Publication number: 20030051740
    Abstract: A method for forming chrome photomasks and phase-shift masks without producing chrome opaque defects. The method involves rinsing the mask blank with dilute acid, preferably nitric or perchloric acid, during processing to form the photomask. When a dry etch is used to form the photomask, the mask blank is rinsed after wet development of the photoresist. When a wet etch is used to form the photomask, the mask blank is rinsed after the wet etch. This method decreases the number of defects per photomask as well as the mask-to-mask variation in the number of defects.
    Type: Application
    Filed: October 29, 2002
    Publication date: March 20, 2003
    Inventors: Virginia Chi-Chuen Chao, Scott A. Estes, Thomas B. Faure, Thomas M. Wagner
  • Patent number: 6494966
    Abstract: A method for removing contaminants from a substrate surface having a pattern formed on the surface. The method involves rinsing the substrate and pattern with water to remove acid reactive material. The substrate and pattern are then washed with an acid whose concentration is too low to attack the material that forms the pattern. Then the substrate is washed with water to remove the acid.
    Type: Grant
    Filed: December 7, 2000
    Date of Patent: December 17, 2002
    Assignee: International Business Machines Corporation
    Inventors: Virginia Chi-Chuen Chao, Scott A. Estes, Thomas B. Faure, Thomas M. Wagner
  • Publication number: 20010001958
    Abstract: A method for forming chrome photomasks and phase-shift masks without producing chrome opaque defects. The method involves rinsing the mask blank with dilute acid, preferably nitric or perchloric acid, during processing to form the photomask. When a dry etch is used to form the photomask, the mask blank is rinsed after wet development of the photoresist. When a wet etch is used to form the photomask, the mask blank is rinsed after the wet etch. This method decreases the number of defects per photomask as well as the mask-to-mask variation in the number of defects.
    Type: Application
    Filed: December 7, 2000
    Publication date: May 31, 2001
    Inventors: Virginia Chi-Chuen Chao, Scott A. Estes, Thomas B. Faure, Thomas M. Wagner
  • Patent number: 6191085
    Abstract: A method is provided for treating a plurality of semiconductor substrates using the same aqueous SC-1 solution which solution removes and/or inhibits contamination of the semiconductor surfaces by metallic ions present in the solution or on the substrate surface comprising a basic solution containing hydrogen peroxide and an oxidation-resistant chelating additive such as CDTA in an amount effective to provide the desired treatment results. The SC-1 solution may be the conventional 5:1:1 (water:NH4OH:H2O2) solution or a dilute solution such as a 5:x:1 to 200:x:l solution wherein x is 0.025 to 2.
    Type: Grant
    Filed: May 10, 1999
    Date of Patent: February 20, 2001
    Assignee: International Business Machines Corporation
    Inventors: Emanuel I. Cooper, Scott A. Estes, Glenn W. Gale, Rangarajan Jagannathan, Harald F. Okorn-Schmidt, David L. Rath
  • Patent number: 6162565
    Abstract: A method for forming chrome photomasks and phase-shift masks without producing chrome opaque defects. The method involves rinsing the mask blank with dilute acid, preferably nitric or perchloric acid, during processing to form the photomask. When a dry etch is used to form the photomask, the mask blank is rinsed after wet development of the photoresist. When a wet etch is used to form the photomask, the mask blank is rinsed after the wet etch. This method decreases the number of defects per photomask as well as the mask-to-mask variation in the number of defects.
    Type: Grant
    Filed: October 23, 1998
    Date of Patent: December 19, 2000
    Assignee: International Business Machines Corporation
    Inventors: Virginia Chi-Chuen Chao, Scott A. Estes, Thomas B. Faure, Thomas M. Wagner
  • Patent number: 5962384
    Abstract: A method is provided for treating a plurality of semiconductor substrates using the same aqueous SC-1 solution which solution removes and/or inhibits contamination of the semiconductor surfaces by metallic ions present in the solution or on the substrate surface comprising a basic solution containing hydrogen peroxide and an oxidation-resistant chelating additive such as CDTA in an amount effective to provide the desired treatment results. The SC-1 solution may be the conventional 5:1:1 (water:NH.sub.4 OH:H.sub.2 O.sub.2) solution or a dilute solution such as a 5:x:1 to 200:x:1 solution wherein x is 0.025 to 2.
    Type: Grant
    Filed: October 28, 1997
    Date of Patent: October 5, 1999
    Assignee: International Business Machines Corporation
    Inventors: Emanuel I. Cooper, Scott A. Estes, Glenn W. Gale, Rangarajan Jagannathan, Harald F. Okorn-Schmidt, David L. Rath
  • Patent number: 5946544
    Abstract: In a circuit board/IC package assembly the die cavity in the IC package body portion is filled with a thermally conductive liquid to substantially facilitate the transfer of operational die heat toward the inner, lid side of the IC package that faces the circuit board. To dissipate the die heat received by the die cavity lid, a spaced series of metal-plated through holes are formed in the circuit board. The metal plating portions of the through holes are engaged with an internal ground plane structure within the circuit board, and are thermally coupled to the IC package die cavity lid. Accordingly, during operation of the IC package, die heat is conducted to the ground plane structure sequentially through the die cavity liquid, the cavity lid, and the metal-plated through holes.
    Type: Grant
    Filed: November 22, 1996
    Date of Patent: August 31, 1999
    Assignee: Dell USA, L.P.
    Inventors: Scott Estes, Deepak Swamy
  • Patent number: 5714789
    Abstract: In a circuit board/IC package assembly the die cavity in the IC package body portion is filled with a thermally conductive liquid to substantially facilitate the transfer of operational die heat toward the inner, lid side of the IC package that faces the circuit board. To dissipate the die heat received by the die cavity lid, a spaced series of metal-plated through holes are formed in the circuit board. The metal plating portions of the through holes are engaged with an internal ground plane structure within the circuit board, and are thermally coupled to the IC package die cavity lid. Accordingly, during operation of the IC package, die heat is conducted to the ground plane structure sequentially through the die cavity liquid, the cavity lid, and the metal-plated through holes.
    Type: Grant
    Filed: November 22, 1996
    Date of Patent: February 3, 1998
    Assignee: Dell U.S.A., L.P.
    Inventors: Scott Estes, Deepak Swamy
  • Patent number: 5685073
    Abstract: A printed circuit board modular assembly is disclosed. The disclosed invention comprises a first printed circuit board having an electronic terminal portion for providing electrical connection to the first printed circuit board; a second printed circuit board having an electrical terminal portion for providing electrical connection to the second printed circuit board; a spacing member disposed between the first and second printed circuit boards; and electrical signal transmission contacts situated on the spacing member for providing electrical connection between the first printed circuit board and the second printed circuit board.
    Type: Grant
    Filed: June 1, 1995
    Date of Patent: November 11, 1997
    Assignee: Compaq Computer Corporation
    Inventors: H. Scott Estes, James J. Ganthier
  • Patent number: 5625227
    Abstract: In a circuit board/IC package assembly the die cavity in the IC package body portion is filled with a thermally conductive liquid to substantially facilitate the transfer of operational die heat toward the inner, lid side of the IC package that faces the circuit board. To dissipate the die heat received by the die cavity lid, a spaced series of metal-plated through holes are formed in the circuit board. The metal plating portions of the through holes are engaged with an internal ground plane structure within the circuit board, and are thermally coupled to the IC package die cavity lid. Accordingly, during operation of the IC package, die heat is conducted to the ground plane structure sequentially through the die cavity liquid, the cavity lid, and the metal-plated through holes.
    Type: Grant
    Filed: January 18, 1995
    Date of Patent: April 29, 1997
    Assignee: Dell USA, L.P.
    Inventors: Scott Estes, Deepak Swamy