Patents by Inventor Scott A. Gilbert

Scott A. Gilbert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230112097
    Abstract: A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.
    Type: Application
    Filed: December 12, 2022
    Publication date: April 13, 2023
    Applicant: Tahoe Research, Ltd.
    Inventors: MD Altaf HOSSAIN, Scott A. GILBERT
  • Patent number: 11528809
    Abstract: A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: December 13, 2022
    Assignee: Tahoe Research, Ltd.
    Inventors: Md Altaf Hossain, Scott A. Gilbert
  • Publication number: 20210185830
    Abstract: A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.
    Type: Application
    Filed: February 26, 2021
    Publication date: June 17, 2021
    Inventors: MD Altaf HOSSAIN, Scott A. GILBERT
  • Patent number: 10980134
    Abstract: A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: April 13, 2021
    Assignee: Intel Corporation
    Inventors: MD Altaf Hossain, Scott A. Gilbert
  • Publication number: 20190230795
    Abstract: A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.
    Type: Application
    Filed: April 1, 2019
    Publication date: July 25, 2019
    Inventors: MD Altaf HOSSAIN, Scott A. GILBERT
  • Patent number: 10297542
    Abstract: A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: MD Altaf Hossain, Scott A. Gilbert
  • Patent number: 10278292
    Abstract: A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: April 30, 2019
    Assignee: Intel Corporation
    Inventors: Md Altaf Hossain, Scott A. Gilbert
  • Patent number: 9799556
    Abstract: A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: October 24, 2017
    Assignee: Intel Corporation
    Inventors: Md Altaf Hossain, Scott A. Gilbert
  • Patent number: 9721882
    Abstract: A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: August 1, 2017
    Assignee: Intel Corporation
    Inventors: MD Altaf Hossain, Scott A. Gilbert
  • Publication number: 20160181145
    Abstract: A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.
    Type: Application
    Filed: February 29, 2016
    Publication date: June 23, 2016
    Inventors: MD Altaf Hossain, Scott A. GILBERT
  • Publication number: 20160128207
    Abstract: A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.
    Type: Application
    Filed: January 11, 2016
    Publication date: May 5, 2016
    Inventors: MD Altaf Hossain, Scott A. Gilbert
  • Patent number: 9293426
    Abstract: A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: March 22, 2016
    Assignee: Intel Corporation
    Inventors: MD Altaf Hossain, Scott A. Gilbert
  • Patent number: 9237659
    Abstract: A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: January 12, 2016
    Assignee: Intel Corporation
    Inventors: MD Altaf Hossain, Scott A. Gilbert
  • Publication number: 20140092572
    Abstract: A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: MD Altaf Hossain, Scott A. Gilbert
  • Publication number: 20140091428
    Abstract: A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: MD Altaf Hossain, Scott A. Gilbert
  • Publication number: 20120161312
    Abstract: Electronic assemblies and their manufacture are described. One assembly includes a substrate and a die on a first side of the substrate. A plurality of non-solder metal bumps are positioned on a second side of the substrate. The assembly also includes a board to which the non-solder metal bumps are coupled. The assembly also includes solder positioned between the board and the substrate, wherein the board is electrically coupled to the substrate through the solder and the bumps. Other embodiments are described and claimed.
    Type: Application
    Filed: December 23, 2010
    Publication date: June 28, 2012
    Inventors: Md Altaf HOSSAIN, Scott A. GILBERT
  • Patent number: 7241147
    Abstract: A socket may receive both ball grid and land grid array packages. Thus, in some embodiments, the early package prototypes, without solder balls, may be packaged in the same socket design that is ultimately used for production devices using ball grid array packaging. Both land grid array and ball grid arrays may be self-centered on the socket in some embodiments. An S-shaped spring contact may be utilized to electrically connect to either solder balls or lands in a wiping action.
    Type: Grant
    Filed: April 12, 2004
    Date of Patent: July 10, 2007
    Assignee: Intel Corporation
    Inventors: Shawn L. Lloyd, John G. Oldendorf, Michael Kochanowski, Scott A. Gilbert