Patents by Inventor Scott A. Gilbert
Scott A. Gilbert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230112097Abstract: A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.Type: ApplicationFiled: December 12, 2022Publication date: April 13, 2023Applicant: Tahoe Research, Ltd.Inventors: MD Altaf HOSSAIN, Scott A. GILBERT
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Patent number: 11528809Abstract: A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.Type: GrantFiled: February 26, 2021Date of Patent: December 13, 2022Assignee: Tahoe Research, Ltd.Inventors: Md Altaf Hossain, Scott A. Gilbert
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Publication number: 20210185830Abstract: A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.Type: ApplicationFiled: February 26, 2021Publication date: June 17, 2021Inventors: MD Altaf HOSSAIN, Scott A. GILBERT
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Patent number: 10980134Abstract: A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.Type: GrantFiled: April 1, 2019Date of Patent: April 13, 2021Assignee: Intel CorporationInventors: MD Altaf Hossain, Scott A. Gilbert
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Publication number: 20190230795Abstract: A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.Type: ApplicationFiled: April 1, 2019Publication date: July 25, 2019Inventors: MD Altaf HOSSAIN, Scott A. GILBERT
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Patent number: 10297542Abstract: A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.Type: GrantFiled: July 31, 2017Date of Patent: May 21, 2019Assignee: Intel CorporationInventors: MD Altaf Hossain, Scott A. Gilbert
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Patent number: 10278292Abstract: A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.Type: GrantFiled: January 11, 2016Date of Patent: April 30, 2019Assignee: Intel CorporationInventors: Md Altaf Hossain, Scott A. Gilbert
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Patent number: 9799556Abstract: A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.Type: GrantFiled: February 29, 2016Date of Patent: October 24, 2017Assignee: Intel CorporationInventors: Md Altaf Hossain, Scott A. Gilbert
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Patent number: 9721882Abstract: A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.Type: GrantFiled: January 30, 2017Date of Patent: August 1, 2017Assignee: Intel CorporationInventors: MD Altaf Hossain, Scott A. Gilbert
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Publication number: 20160181145Abstract: A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.Type: ApplicationFiled: February 29, 2016Publication date: June 23, 2016Inventors: MD Altaf Hossain, Scott A. GILBERT
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Publication number: 20160128207Abstract: A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.Type: ApplicationFiled: January 11, 2016Publication date: May 5, 2016Inventors: MD Altaf Hossain, Scott A. Gilbert
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Patent number: 9293426Abstract: A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.Type: GrantFiled: September 28, 2012Date of Patent: March 22, 2016Assignee: Intel CorporationInventors: MD Altaf Hossain, Scott A. Gilbert
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Patent number: 9237659Abstract: A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.Type: GrantFiled: September 28, 2012Date of Patent: January 12, 2016Assignee: Intel CorporationInventors: MD Altaf Hossain, Scott A. Gilbert
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Publication number: 20140092572Abstract: A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Inventors: MD Altaf Hossain, Scott A. Gilbert
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Publication number: 20140091428Abstract: A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Inventors: MD Altaf Hossain, Scott A. Gilbert
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Publication number: 20120161312Abstract: Electronic assemblies and their manufacture are described. One assembly includes a substrate and a die on a first side of the substrate. A plurality of non-solder metal bumps are positioned on a second side of the substrate. The assembly also includes a board to which the non-solder metal bumps are coupled. The assembly also includes solder positioned between the board and the substrate, wherein the board is electrically coupled to the substrate through the solder and the bumps. Other embodiments are described and claimed.Type: ApplicationFiled: December 23, 2010Publication date: June 28, 2012Inventors: Md Altaf HOSSAIN, Scott A. GILBERT
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Patent number: 7241147Abstract: A socket may receive both ball grid and land grid array packages. Thus, in some embodiments, the early package prototypes, without solder balls, may be packaged in the same socket design that is ultimately used for production devices using ball grid array packaging. Both land grid array and ball grid arrays may be self-centered on the socket in some embodiments. An S-shaped spring contact may be utilized to electrically connect to either solder balls or lands in a wiping action.Type: GrantFiled: April 12, 2004Date of Patent: July 10, 2007Assignee: Intel CorporationInventors: Shawn L. Lloyd, John G. Oldendorf, Michael Kochanowski, Scott A. Gilbert