Patents by Inventor Scott A. Hauck

Scott A. Hauck has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9590655
    Abstract: A method of lossless data compression includes receiving a set of parallel data strings; determining compression hash values for each of the parallel data strings; determining bit matches among portions of each of the parallel data strings based, at least in part, on the compression hash values; selecting among literals and the bit matches for each of the parallel data strings; and applying Huffman encoding to the selected literals or the selected bit matches.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: March 7, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Joo-Young Kim, Douglas C. Burger, Jeremy Halden Fowers, Scott A. Hauck
  • Publication number: 20160285473
    Abstract: A method of lossless data compression includes receiving a set of parallel data strings; determining compression hash values for each of the parallel data strings; determining bit matches among portions of each of the parallel data strings based, at least in part, on the compression hash values; selecting among literals and the bit matches for each of the parallel data strings; and applying Huffman encoding to the selected literals or the selected bit matches.
    Type: Application
    Filed: June 12, 2015
    Publication date: September 29, 2016
    Inventors: Joo-Young Kim, Douglas C. Burger, Jeremy Halden Fowers, Scott A. Hauck
  • Patent number: 5367209
    Abstract: A field programmable gate array (FPGA) including both routing and logic blocks (RLBs) and routing and arbiter blocks (RABs) is disclosed. The RABs are periodically placed throughout the FPGA and operate either to arbitrate the arrival of simultaneous signals or to synchronize simultaneous signals. In addition, each of the RLBs are capable of operating in accordance with two clock signals and an asynchronous initialization. The combination of the RLBs and RABs allow the FPGA to operate synchronously and asynchronously.
    Type: Grant
    Filed: April 30, 1993
    Date of Patent: November 22, 1994
    Inventors: Scott A. Hauck, Gaetano Borriello, Steven M. Burns, William H. C. Ebeling