Abstract: The present application provides a method and apparatus for supporting denormal numbers in a floating point multiply-add unit (FMAC). One embodiment of the FMAC is configurable to add a product of first and second operands to a third operand. This embodiment of the FMAC is configurable to determine a minimum exponent shift for a sum of the product and the third operand by subtracting a minimum normal exponent from a product exponent of the product. This embodiment of the FMAC is also configurable to cause bits representing the sum to be left shifted by the minimum exponent shift if a third exponent of the third operand is less than or equal to the product exponent and the minimum exponent shift is less than or equal to a predicted left shift for the sum.

Abstract: The disclosed embodiments relate to apparatus for accurately, efficiently and quickly executing a multiplication instruction. The disclosed embodiments can provide a multiplier module having an optimized layout that can help speed up computation of a result during a multiply operation so that cycle delay can be reduced and so that power consumption can be reduced.

Abstract: The present application provides a method and apparatus for supporting denormal numbers in a floating point multiply-add unit (FMAC). One embodiment of the FMAC is configurable to add a product of first and second operands to a third operand. This embodiment of the FMAC is configurable to determine a minimum exponent shift for a sum of the product and the third operand by subtracting a minimum normal exponent from a product exponent of the product. This embodiment of the FMAC is also configurable to cause bits representing the sum to be left shifted by the minimum exponent shift if a third exponent of the third operand is less than or equal to the product exponent and the minimum exponent shift is less than or equal to a predicted left shift for the sum.

Abstract: The disclosed embodiments relate to apparatus for accurately, efficiently and quickly executing a multiplication instruction. The disclosed embodiments can provide a multiplier module having an optimized layout that can help speed up computation of a result during a multiply operation so that cycle delay can be reduced and so that power consumption can be reduced.

Abstract: Sum and carry signals are formed representing a product of a first and a second operand. A bias signal is formed having a value determined by a sign of a product of the first and the second operand. An output signal is provided based on an addition of the sum signal, the carry signal, a sign-extended addend, and the bias signal. A portion of the output signal, a saturated minimum value, or a saturated maximum value, is selected as a final result based on the sign of the product and a sign of the output signal.

Abstract: A merged compressor flip-flop circuit is provided.

Abstract: A method of executing a program instruction is disclosed. An instruction operand stored at a register of a register file is accessed by an execution unit using multiple access requests. A first portion of the execution unit provides a first access request to a first access port of the register file to access a first portion of the instruction operand. A second portion of the execution unit provides a second access request to a second access port of the register file to access a second portion of the instruction operand. The register file can be configured into physically separate portions.

Abstract: Sum and carry signals are formed representing a product of a first and a second operand. A bias signal is formed having a value determined by a sign of a product of the first and the second operand. An output signal is provided based on an addition of the sum signal, the carry signal, a sign-extended addend, and the bias signal. A portion of the output signal, a saturated minimum value, or a saturated maximum value, is selected as a final result based on the sign of the product and a sign of the output signal.

Abstract: In a hardware floating point adder, each operand exponent is logically divided into fields. The corresponding fields of each exponent are input to a separate shift logic circuit which determines a relative amount to shift the operand mantissa without reference to any carry bit from a lower order field. Both mantissas are potentially shifted, each by one or more shift logic circuit outputs, making it possible to perform some of the shifts simultaneously. Using 11 bit exponents in accordance with ANSI/IEEE Standard 754-1985, double format for 64-bit numbers, operand registers are logically divided into: field #3, consisting the lowest two order bits; field #2 consisting of the next lowest two order bits after the first two; and field #1 consisting of the highest 7 order bits. The shift logic circuit for field #3 shifts and Operand A mantissa, right or left, 0, 1, 2 or 3 bits. The shift logic circuit for field #2 simultaneously shifts an Operand B mantissa, right or left, 0, 4, 8 or 12 bits.

Abstract: An apparatus and method for determining the difference between two exponents of two floating point numbers is disclosed. The exponent of each number is split into two portions. A high portion contains the most significant bits and a low portion contains the least significant bits. The number of bits in the low portion is related to the number of bits in the fraction portion of each floating point number. To determine differences that require a shift in one of the exponenets, one of the differences between the low portions of the exponents is selected based upon which of several conditions are found with respect to the difference between the high portion. Advantageously, a set of adders which are as wide as the number of bits in the low portion of each exponent are used.

Abstract: A tightly-coupled main processor and coprocessor overlap the execution of sequential instructions when apparent sequential operation and precise exception interrupts can be assured. Logic detects all conditions under which these criteria might potentially be violated in the coprocessor before it has finished performing an instruction, and holds off the main processor from executing a subsequent instruction.

Abstract: Apparatus for enhancing certain floating point arithmetic operations, by examining the initial operands and the exponent and fractional results and predicting when the steps of postnormalization and rounding can be skipped. The fraction result format enables a prediction of normalization and rounding under each of the addition, subtraction and multiplication possibilities, and under each of the various choices of rounding mode which are used in floating point arithmetic.

Abstract: A method and apparatus for processing postnormalization and rounding in parallel in floating point arithmetic circuits. The fractional result of a floating point arithmetic operation is simultaneously passed to a normalized circuit and a round circuit, and the first two bit positions of the fractional result are examined. If the 2-bit format is 1.X the round circuit is activated; if the 2-bit format is 0.1X the fractional result is shifted left one position and the round circuit is activated; if the 2-bit format is in neither of the above formats the normalize circuit is activated. In no event is it necessary to activate sequentially the normalize circuit and the round circuit.

Abstract: An apparatus for determining the correct value to be assigned to the "sticky-bit" (S) position as a consequence of an arithmetic floating point multiply, divide or square root operation. The apparatus measures the number of trailing zeroes in the operand registers, performs a sum or difference calculation of these values, and compares the result with a third value to determine the sticky-bit value.