Patents by Inventor Scott A. Johannesmeyer

Scott A. Johannesmeyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of preventing seam defects in isolated lines
    Patent number: 6709974
    Abstract: A method of preventing seam defects on narrow, isolated lines of 0.3 micron or less during CMP process is provided. The solution is to change the size of features of dummy metal structures on the same layer as the metal layer to have a width that is about 0.6 micron or less so that during the electroplating the deposition rate in the features is similar to the narrow, isolated lines. The density, shape, and proximity of the dummy metal structures further prevents the seam defects during CMP processing by preventing Galvanic corrosion.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: March 23, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: David Permana, Jiong-Ping Lu, Albert Cheng, Jeff A. West, Brock W. Fairchild, Scott A. Johannesmeyer, Chris M. Bowles, Thomas D. Bonifield, Rajesh Tiwari
  • System and method for processing a transistor channel layout
    Patent number: 6668366
    Abstract: A system for processing a transistor channel layout includes a processor coupled to an input device, an output device, a memory, and a data retrieval device. The memory stores input layout data defining a transistor channel layout having a bend between a first end and a second end. The memory further stores contour adjustment data. The processor adjusts the bend of the transistor channel layout according to the contour adjustment data and generates output layout data defining the adjusted transistor channel layout.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: December 23, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Hongmei Liao, Scott A. Johannesmeyer
  • Method of preventing seam defects in isolated lines
    Publication number: 20030199150
    Abstract: A method of preventing seam defects on narrow, isolated lines of 0.3 micron or less during CMP process is provided. The solution is to change the size of features of dummy metal structures on the same layer as the metal layer to have a width that is about 0.6 micron or less so that during the electroplating the deposition rate in the features is similar to the narrow, isolated lines. The density, shape, and proximity of the dummy metal structures further prevents the seam defects during CMP processing by preventing Galvanic corrosion.
    Type: Application
    Filed: December 19, 2002
    Publication date: October 23, 2003
    Inventors: David Permana, Jiong-Ping Lu, Albert Cheng, Jeff A. West, Brock W. Fairchild, Scott A. Johannesmeyer, Chris M. Bowles, Thomas D. Bonifield, Rajesh Tiwari
  • System and method for processing a transistor channel layout
    Publication number: 20020023254
    Abstract: A system for processing a transistor channel layout includes a processor coupled to an input device, an output device, a memory, and a data retrieval device. The memory stores input layout data defining a transistor channel layout having a bend between a first end and a second end. The memory further stores contour adjustment data. The processor adjusts the bend of the transistor channel layout according to the contour adjustment data and generates output layout data defining the adjusted transistor channel layout.
    Type: Application
    Filed: August 17, 2001
    Publication date: February 21, 2002
    Inventors: Hongmei Liao, Scott A. Johannesmeyer