Abstract: An apparatus, system, and method are disclosed for cache synchronization within a multi-tier system having multiple client-server relationships. The apparatus includes a pre-synchronization module, a locking module, and a synchronization module. The pre-synchronization module receives a pre-synchronization call from an upstream node coupled to a first downstream node. The locking module locks a first cache coupled to the first downstream node in response to a synchronization call from the upstream node. The synchronization module synchronizes source data on the upstream node with cached data on the first cache. The apparatus also may include a post-synchronization module to perform any necessary cleanup activities. Advantageously, the apparatus, system, and method reduce the likelihood of a system deadlock due to premature locking of the first downstream cache, which prevents a subsequent downstream cache from synchronizing with the first cache.

Abstract: A method and system for tracking usage of memory in a computer system is provided. Arguments for both the size of a memory allocation and the type of memory being allocated are reserved in a fixed location. A first fixed location is reserved for small memory allocations, i.e. less than one page, and a second fixed location is reserved for large memory allocations, i.e. one page or larger. The fixed location is selected based upon a determination of the size of an allocation required by a calling application. Upon receipt of a memory allocation request by the calling application, a pointer is returned to the calling application identifying the fixed location. Similarly, upon release of memory by the calling application, a counter is decremented to track the amount of memory in use by the application.

Abstract: Systems and methods for transferring data. A circuit transfers information between two buses using different signal voltage levels and multiplexes signals applied to the second bus over multiple devices coupled thereto. The data on a first data bus is transferred at a first voltage level and the data on a second data bus is transferred at a second voltage level. For example, the first data bus may transfer data at 3.3V and the second data bus may transfer data at 5V. A logic device (e.g., a CPLD) is connected between the first and the second data buses for transferring the data between the first and second voltage levels. The logic device is also configured for multiplexing the data with the second voltage level between first and second devices (e.g., one or more LEDs and/or NVSRAMs) connected to the second data bus.

Abstract: A universal interface circuit and an associated method are provided that can supply a computer logic circuit, such as the components mounted upon an adapter card, with first and second inputs having first and second predetermined voltage levels, respectively, based upon power drawn from both first and second supply voltages. The interface circuit typically includes a first power supply circuit for providing the first input having the first predetermined voltage level in response to the first supply voltage. Additionally, the interface surface includes a regulator for generating an output having the second predetermined voltage level in response to the first supply voltage. The interface circuit further includes a second power supply circuit for providing an output that also has the second predetermined voltage level, albeit in response to the second supply voltage.

Abstract: Systems and methods for transferring data. A circuit transfers information between two buses using different signal voltage levels and multiplexes signals applied to the second bus over multiple devices coupled thereto. The data on a first data bus is transferred at a first voltage level and the data on a second data bus is transferred at a second voltage level. For example, the first data bus may transfer data at 3.3V and the second data bus may transfer data at 5V. A logic device (e.g., a CPLD) is connected between the first and the second data buses for transferring the data between the first and second voltage levels. The logic device is also configured for multiplexing the data with the second voltage level between first and second devices (e.g., one or more LEDs and/or NVSRAMs) connected to the second data bus.

Abstract: A transportable memory apparatus including cache memory and a backup battery is provided that is capable of being removed from a first computer system and installed within a second computer system. The transportable memory apparatus includes a control bus that provides appropriate signals such that the presence and status of the transportable memory apparatus can be detected in order to permit the computer system that includes the transportable memory apparatus to be appropriately initialized. As such, methods for initializing a computer system that may include a transportable memory apparatus are also provided.

Abstract: A transportable memory apparatus including cache memory and a backup battery is provided that is capable of being removed from a first computer system and installed within a second computer system. The transportable memory apparatus includes a control bus that provides appropriate signals such that the presence and status of the transportable memory apparatus can be detected in order to permit the computer system that includes the transportable memory apparatus to be appropriately initialized. As such, methods for initializing a computer system that may include a transportable memory apparatus are also provided.

Abstract: A transportable memory apparatus including cache memory and a backup battery is provided that is capable of being removed from a first computer system and installed within a second computer system. The transportable memory apparatus includes a control bus that provides appropriate signals such that the presence and status of the transportable memory apparatus can be detected in order to permit the computer system that includes the transportable memory apparatus to be appropriately initialized. As such, methods for initializing a computer system that may include a transportable memory apparatus are also provided.