Patents by Inventor Scott A. Rumery

Scott A. Rumery has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Passivation for Group III-V Semiconductor Devices Having a Plated Metal Layer over an Interlayer Dielectric Layer
    Publication number: 20150048484
    Abstract: A semiconductor device that includes a Group III-V semiconductor substrate, circuit elements in and on the substrate, a first metal layer over the substrate, and an interlayer dielectric (ILD) layer. The ILD layer defines a via that extends through it to the first metal layer. Over the ILD layer is thick second metal layer and a passivation layer. The second metal layer includes an interconnect that extends through the via into contact with the first metal layer. The second metal layer is patterned to define at least one conductor. The passivation layer covers the second metal layer and the interlayer dielectric layer, and includes stacked regions of dielectric material. Ones of the regions under tensile stress alternate with ones of the regions under compressive stress, such that the passivation layer is subject to net compressive stress.
    Type: Application
    Filed: August 13, 2013
    Publication date: February 19, 2015
    Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Nathan Perkins, Jonathan Abrokwah, Ricky Snyder, Scott A. Rumery, Robert G. Long
  • Passivation for group III-V semiconductor devices having a plated metal layer over an interlayer dielectric layer
    Patent number: 8941218
    Abstract: A semiconductor device that includes a Group III-V semiconductor substrate, circuit elements in and on the substrate, a first metal layer over the substrate, and an interlayer dielectric (ILD) layer. The ILD layer defines a via that extends through it to the first metal layer. Over the ILD layer is thick second metal layer and a passivation layer. The second metal layer includes an interconnect that extends through the via into contact with the first metal layer. The second metal layer is patterned to define at least one conductor. The passivation layer covers the second metal layer and the interlayer dielectric layer, and includes stacked regions of dielectric material. Ones of the regions under tensile stress alternate with ones of the regions under compressive stress, such that the passivation layer is subject to net compressive stress.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: January 27, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Nathan Perkins, Jonathan Abrokwah, Ricky Snyder, Scott A. Rumery, Robert G. Long