Abstract: A set of threshold voltage distribution width measurements are obtained for a block in a memory device. An endurance estimate is determined for the block based on the threshold voltage distribution width measurements. The endurance estimate comprises an indication of an estimated number of program/erase cycles during which data can be reliably stored by the block. One or more parameters of the block are managed based on the endurance estimate.

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a set of write operations on a first block in a first plane of the memory device and on a second block in a second plane of the memory device, performing a program verification check on the first block, responsive to determining that the first block fails the program verification check, incrementing a counter value associated with the second block; responsive to the counter value satisfying a threshold criterion, performing a failure verification operation on the second block, and responsive to determining that the second block fails the failure verification operation, retiring the second block.

Abstract: A set of threshold voltage distribution width measurements are obtained for a block in a memory device. An endurance estimate is determined for the block based on the threshold voltage distribution width measurements. The endurance estimate comprises an indication of an estimated number of program/erase cycles during which data can be reliably stored by the block. One or more parameters of the block are managed based on the endurance estimate.

Abstract: A trigger condition associated with latent read disturb in a memory device is detected. In response to detecting the trigger condition associated with latent read disturb, one or more blocks in the memory device that are impacted by the trigger condition are placed in a stable state to mitigate latent read disturb in the one or more blocks.

Abstract: A log of error events associated with a memory device is maintained. Each error event included in the log is associated with one of multiple physical locations within the memory device. A physical location within the memory device is identified for background scanning based on the log of error events. A background scan is performed on the physical location identified based on the log of error events.

Abstract: A failure of a block among a set of blocks of a memory device of a memory subsystem is detected. Based on detecting the failure of the block, the block is evaluated for reuse. The block is designated for reuse based on a result of the evaluating of the block. The block is allocated to a task based on the block being designated for reuse.

Abstract: Disclosed in some examples are methods, systems, devices, memory controllers, memory dies, memory devices, and machine-readable mediums that allow for efficient updating of software instructions of the memory die. In some examples, the controller of the memory device may cause the software instructions of one or more memory dies to be updated by causing the page buffers of the one or more memory dies to be loaded with updated software instructions and subsequently issuing a command to the memory die to update the software instructions from the page buffer.

Abstract: A failed erase operation is detected at a memory block of a memory device. Based on detecting the failed erase operation at the memory block, data on the memory block is destroyed using a data destruction algorithm that corrupts data stored by one or more cells of the block. The data on the memory block is verified to be destroyed. A passing data destruction status for the memory block is provided based on verifying the data on the memory block is destroyed.

Abstract: A read operation is performed on a memory device in accordance with a pass-through voltage setting that defines a pass-through voltage applied to one or more cells of the memory device during read operations. A number of zero bits read from the memory device based on the read operation are counted and compared with a threshold value. Based on the number of zero bits exceeding the threshold value, the pass-through voltage is increased by adjusting the pass-through voltage setting.

Abstract: NAND memory devices are described that utilize higher read-margin cell types to provide a more granular read disturb indicator without utilizing dummy cells. For example, a NAND architecture may have some cells that are configured as SLC or MLC cells. SLC or MLC cells have more read disturb margin—that is these cells can withstand more read disturb current leakage into the cell before a bit error occurs than TLC or QLC cells. These higher margin cells may serve as the read disturb indicator for a group of cells that have a comparatively lower read disturb margin. Since there are more pages of these higher margin cells than there are pages of dummy cells, these indicators may serve a smaller group of pages than the dummy pages. This reduces the time needed to complete a read disturb scan as fewer pages need to be scanned.

Abstract: Systems and methods are disclosed, including determining whether to write dummy data to a first physical page of memory cells of a storage system, such as in response to a detected asynchronous power loss (APL) at the storage system, using a determined number of ones stored in the first physical page.

Abstract: A log of error events associated with a memory device is maintained. Each error event included in the log is associated with one of multiple physical locations within the memory device. A physical location within the memory device is identified for background scanning based on the log of error events. A background scan is performed on the physical location identified based on the log of error events.

Abstract: Various embodiments provide for adjusting (or adapting) a program voltage step used to program a memory cell by a program algorithm after the program algorithm resumes from a suspension, where the program voltage step is adjusted (or adapted) based on one or more factors.

Abstract: Disclosed in some examples are methods, systems, devices, memory controllers, memory dies, memory devices, and machine-readable mediums that allow for efficient updating of software instructions of the memory die. In some examples, the controller of the memory device may cause the software instructions of one or more memory dies to be updated by causing the page buffers of the one or more memory dies to be loaded with updated software instructions and subsequently issuing a command to the memory die to update the software instructions from the page buffer.

Abstract: Various embodiments provide for adjusting (or adapting) a program voltage step used to program a memory cell by a program algorithm after the program algorithm resumes from a suspension, where the program voltage step is adjusted (or adapted) based on one or more factors.

Abstract: A read operation is performed on a memory device in accordance with a pass-through voltage setting that defines a pass-through voltage applied to one or more cells of the memory device during read operations. A number of zero bits read from the memory device based on the read operation are counted and compared with a threshold value. Based on the number of zero bits exceeding the threshold value, the pass-through voltage is increased by adjusting the pass-through voltage setting.

Abstract: A log of error events associated with a memory device is maintained. Each error event included in the log is associated with one of multiple physical locations within the memory device. A physical location within the memory device is identified for background scanning based on the log of error events. A background scan is performed on the physical location identified based on the log of error events.

Abstract: Disclosed in some examples are methods, systems, devices, memory controllers, memory dies, memory devices, and machine-readable mediums that allow for efficient updating of software instructions of the memory die. In some examples, the controller of the memory device may cause the software instructions of one or more memory dies to be updated by causing the page buffers of the one or more memory dies to be loaded with updated software instructions and subsequently issuing a command to the memory die to update the software instructions from the page buffer.

Abstract: A trigger condition associated with latent read disturb in a memory device is detected. In response to detecting the trigger condition associated with latent read disturb, one or more blocks in the memory device that are impacted by the trigger condition are placed in a stable state to mitigate latent read disturb in the one or more blocks.

Abstract: A log of error events associated with a memory device is maintained. Each error event included in the log is associated with one of multiple physical locations within the memory device. A physical location within the memory device is identified for background scanning based on the log of error events. A background scan is performed on the physical location identified based on the log of error events.