Abstract: A computer-implemented method for switching between a full space and a subspace across multiple address spaces is described. A non-limiting example of the computer-implemented method includes determining, by a processor, that switching between the full space and the subspace is enabled by examining a bit in a control register. The method determines, by the processor, that there is a new context different from an existing context based on the bit in the control register indicating that switching is enabled and switches, by the processor, the context of the multiple spaces based on determining that the new context is different from the existing context.

Abstract: Provided are a computer program product, system, and method for sharing alias addresses among logical devices by a host accessing logical devices provisioned with a capacity from physical devices managed by a control unit. The host establishes with the control unit an association of logical devices and alias addresses assigned to the logical devices, wherein the alias addresses are associated with an alias management group. Alias address pool information is generated indicating each of the logical devices and their assigned alias addresses indicated in the association. The host uses from the alias address pool information any one of the alias addresses in the alias address pool information to access any of the logical devices associated with the same alias management group as the alias address.

Abstract: An aspect includes determining, via a processor, context attributes of a storage. Data address translation (DAT) tables are created, via the processor, to map virtual addresses to real addresses within the storage. When detecting, via the processor, that a context attribute of the storage has changed, and the DAT tables are updated based at least in part on the changed context attributes of the storage.

Abstract: A computer-implemented method for implementing a full space dynamic address translation (“DAT”) structure and a subspace DAT structure is provided. A non-limiting example of the computer-implemented method includes determining, by a processor, that switching between the full space DAT structure and the subspace DAT structure is enabled by examining a bit in a control register. The method determines, by the processor, that there is a new context different from an existing context based on the bit in the control register indicating that switching is enabled, and switches, by the processor, the context of the DAT structures based on determining that the new context is different from the existing context.

Abstract: Examples of techniques for sensitive data redaction in a memory dump are described herein. An aspect includes, based on a dump of a virtual address space being triggered, receiving a primary dump corresponding to the virtual address space, the primary dump including one or more tagged memory pages. Another aspect includes identifying, by a sensitive data identification module, sensitive data that is located outside of the of the one or more tagged memory pages in the primary dump. Another aspect includes redacting data corresponding to the sensitive data and the one or more tagged memory pages to determine a redacted dump.

Abstract: A system and method of implementing a firm channel in a computer system are provided. The method including identifying at least one of a channel and a channel path ID (CHPID) as a first firm channel, automatically defining a logical path between a first device and a second device using the first firm channel, and storing the logical path in a configuration file of the computer system, wherein the logical path is accessible at system initialization.

Abstract: Examples of techniques for memory tagging for sensitive data redaction in a memory dump are described herein. An aspect includes receiving a first call to a memory tagging application programming interface (API) from an application, wherein the first call designates a virtual memory page belonging to the application as containing sensitive data. Another aspect includes, based on the first call to the memory tagging API, tagging a physical memory page corresponding to the virtual memory page as sensitive.

Abstract: A computer-implemented method, according to one approach, includes: receiving a first request to perform a write operation from a host, and performing the write operation. Metadata corresponding to the first request is sent to the secondary data storage device, and metadata corresponding to a second request to perform the write operation is received from the secondary data storage device, where the second request was received at the secondary data storage device from the host. The metadata corresponding to the first and second requests is used to determine whether the write operation has been mirrored across the primary and secondary data storage devices. In response to determining that the write operation has been mirrored across the primary and secondary data storage devices, a response is sent to the secondary data storage device which indicates that the write operation has been reconciled across the primary and secondary data storage devices.

Abstract: Examples of techniques for sensitive data redaction in a memory dump are described herein. An aspect includes, based on a dump of a virtual address space being triggered, receiving a primary dump corresponding to the virtual address space, the primary dump including one or more tagged memory pages. Another aspect includes identifying, by a sensitive data identification module, sensitive data that is located outside of the of the one or more tagged memory pages in the primary dump. Another aspect includes redacting data corresponding to the sensitive data and the one or more tagged memory pages to determine a redacted dump.

Abstract: Examples of techniques for memory tagging for sensitive data redaction in a memory dump are described herein. An aspect includes receiving a first call to a memory tagging application programming interface (API) from an application, wherein the first call designates a virtual memory page belonging to the application as containing sensitive data.

Abstract: Aspects of the invention include receiving a request to obtain data located in an address space to diagnose a computer error. It is determined whether a threshold number of resources are available to obtain the data. Based on determining that the threshold number of resources is available to obtain the data, a priority level of the computer program is assessed. A number of threads to assign to a workload to obtain the data from the address space is determined based at least in part on the priority level of the computer program. The determined number of threads are assigned to the workload. The workload is divided into a number of parallel units equal to the number of threads assigned to the workload. The parallel units of the workload are executed by the assigned threads to capture the data in the address space. The captured data is stored.

Abstract: A computer-implemented method, according to one approach, includes: receiving a first request to perform a write operation from a host, and performing the write operation. Metadata corresponding to the first request is sent to the secondary data storage device, and metadata corresponding to a second request to perform the write operation is received from the secondary data storage device, where the second request was received at the secondary data storage device from the host. The metadata corresponding to the first and second requests is used to determine whether the write operation has been mirrored across the primary and secondary data storage devices. In response to determining that the write operation has been mirrored across the primary and secondary data storage devices, a response is sent to the secondary data storage device which indicates that the write operation has been reconciled across the primary and secondary data storage devices.

Abstract: An aspect includes determining, via a processor, context attributes of a storage. Data address translation (DAT) tables are created, via the processor, to map virtual addresses to real addresses within the storage. When detecting, via the processor, that a context attribute of the storage has changed, and the DAT tables are updated based at least in part on the changed context attributes of the storage.

Abstract: One general aspect of device reservation state preservation in accordance with the present description, provides for an intermediate reservation state, referred to herein as a “peer” reservation state, which may be maintained by a storage controller in the event of a total loss of communication connectivity to the reserving host so long as a peer or partner storage controller of a mirror relationship still has communication connectivity to the host. The peer reservation state as used herein, is a reservation state intermediate between a full reservation state for a device, and a fully released state in which a reservation of the device has been completely released. Other features and aspects may be realized, depending upon the particular application.

Abstract: A non-limiting example computer-implemented method includes receiving instructions to switch an operational context of a dynamic address translation (DAT) structure to a new operational context. It is determined if context switching has been enabled within the DAT structure. Based on determining that context switching is enabled, it is determined if the new operational context of the DAT structure is different than a current operational context of the DAT structure. It is chosen whether to switch to a full operational context based on the new operational context being different than the current operational context. If the full operational context is used, a full space DAT structure is set up and a private space bit is set to OFF, and if the full operational context is not used, a partial space DAT structure is set up and the private space bit is set to ON.

Abstract: A computer-implemented method for implementing a full space dynamic address translation (“DAT”) structure and a subspace DAT structure is provided. A non-limiting example of the computer-implemented method includes determining, by a processor, that switching between the full space DAT structure and the subspace DAT structure is enabled by examining a bit in a control register. The method determines, by the processor, that there is a new context different from an existing context based on the bit in the control register indicating that switching is enabled, and switches, by the processor, the context of the DAT structures based on determining that the new context is different from the existing context.

Abstract: An aspect includes determining, via a processor, context attributes of a storage. Data address translation (DAT) tables are created, via the processor, to map virtual addresses to real addresses within the storage. When detecting, via the processor, that a context attribute of the storage has changed, and the DAT tables are updated based at least in part on the changed context attributes of the storage.

Abstract: A computer-implemented method for switching between a full space and a subspace across multiple address spaces is described. A non-limiting example of the computer-implemented method includes determining, by a processor, that switching between the full space and the subspace is enabled by examining a bit in a control register. The method determines, by the processor, that there is a new context different from an existing context based on the bit in the control register indicating that switching is enabled and switches, by the processor, the context of the multiple spaces based on determining that the new context is different from the existing context.

Abstract: A method, system, and computer program product are described for a machine selecting a selected adapter among two or more adapters that perform a same function. The method includes generating a request, at the machine, for the function, and calculating a time indicator associated with each of the two or more adapters based on a respective adapter queue time factor (QTF) associated with each of the two or more adapters, the adapter QTF associated with each of the two or more adapters being a computed value. The method also includes selecting the selected adapter and submitting one or more requests to the selected adapter of the two or more adapters to perform the function based on a comparison of the time indicator associated with each of the two or more adapters.

Abstract: Embodiments of dynamically increasing the resources for a partition to compensate for an input/output (I/O) recovery event are provided. An aspect includes allocating a first set of resources to a partition that is hosted on a data processing system. Another aspect includes operating the partition on the data processing system using the first set of resources. Another aspect includes, based on detection of an input/output (I/O) recovery event associated with operation of the partition, determining a compensation for the I/O recovery event. Another aspect includes allocating a second set of resources in addition to the first set of resources to the partition, the second set of resources corresponding to the compensation for the I/O recovery event. Another aspect includes operating the partition on the data processing system using the first set of resources and the second set of resources.