Abstract: Disclosed is a structure having anchor vias for improved backside metal adhesion and an associated method for the structure's fabrication. The structure includes at least one anchor via disposed in at least one corner of a semiconductor substrate. A metal filler may be formed within the at least one anchor via, the metal filler having a protruding portion extending from a backside of the semiconductor substrate. The structure may further include a backside metal layer on a bottom surface of the semiconductor substrate, the backside metal layer being bonded to the protruding portion of the metal filler in the at least one anchor via. The at least one anchor via may include a cluster of anchor vias, a plurality of anchor vias disposed in a straight line and/or in a staggered configuration along a periphery of the semiconductor substrate.

Abstract: Disclosed is a structure having anchor vias for improved backside metal adhesion and an associated method for the structure's fabrication. The structure includes at least one anchor via disposed in at least one corner of a semiconductor substrate. A metal filler may be formed within the at least one anchor via, the metal filler having a protruding portion extending from a backside of the semiconductor substrate. The structure may further include a backside metal layer on a bottom surface of the semiconductor substrate, the backside metal layer being bonded to the protruding portion of the metal filler in the at least one anchor via. The at least one anchor via may include a cluster of anchor vias, a plurality of anchor vias disposed in a straight line and/or in a staggered configuration along a periphery of the semiconductor substrate.

Abstract: A controllable, piecewise linear gain circuit includes a first field effect transistor (FET), the drain of which is connected to a first source of bias voltage and the gate of which is connected to the input to the circuit. A first capacitor is connected between the gate of the FET and a common ground. The drain of a second FET is connected to the gate of the first FET, while the gate of the second FET is connected to a second source of bias voltage. A second capacitor is connected between the source of the second FET and the common ground. With this configuration, the output voltage of the circuit may be measured across an output resistance connected between the common ground and the source of the first FET, such that the second FET will turn on and connect the second capacitor to the output of the circuit when a predetermined amount of charge has accumulated on the first capacitor, thereby reducing the gain of the circuit.