Patents by Inventor Scott B. Tuttle

Scott B. Tuttle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10254962
    Abstract: In one embodiment, a computer-implemented method includes producing one or more clean frames by clearing a batch of one or more frames for use in backing virtual memory pages. The producing the one or more clean frames may be performed asynchronously from a unit of work being performed by a processor. The one or more clean frames may be added to a clean frame queue, where the clean frame queue includes a plurality of clean frames that have been cleared. A first request may be received, from the processor, for a frame for use in backing a virtual memory page of the unit of work. A clean frame, of the one or more clean frames, may be removed from the clean frame queue, responsive to the first request. The clean frame may be delivered to the processor, responsive to the first request.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: April 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert Miller, Jr., Steven M. Partlow, Thomas F. Rankin, Scott B. Tuttle, Elpida Tzortzatos
  • Patent number: 10216518
    Abstract: Embodiments of the present invention provide systems and methods for clearing specified blocks of main storage. In one embodiment, an EADM start subchannel is executed. The instructions of the execution of the EADM start subchannel may include a SAP receiving an ADM request block, which specifies a main-storage-clearing operation command. The address and size of a block of main memory to be cleared by the SAP is specified in an MSB designated by the ADM request block.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Anthony F. Coneski, Beth A. Glendening, Dan F. Greiner, Peter G. Sutton, Scott B. Tuttle, Elpida Tzortzatos
  • Patent number: 10216517
    Abstract: Embodiments of the present invention provide systems and methods for clearing specified blocks of main storage. In one embodiment, an EADM start subchannel is executed. The instructions of the execution of the EADM start subchannel may include a SAP receiving an ADM request block, which specifies a main-storage-clearing operation command. The address and size of a block of main memory to be cleared by the SAP is specified in an MSB designated by the ADM request block.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Anthony F. Coneski, Beth A. Glendening, Dan F. Greiner, Peter G. Sutton, Scott B. Tuttle, Elpida Tzortzatos
  • Publication number: 20180275879
    Abstract: In one embodiment, a computer-implemented method includes producing one or more clean frames by clearing a batch of one or more frames for use in backing virtual memory pages. The producing the one or more clean frames may be performed asynchronously from a unit of work being performed by a processor. The one or more clean frames may be added to a clean frame queue, where the clean frame queue includes a plurality of clean frames that have been cleared. A first request may be received, from the processor, for a frame for use in backing a virtual memory page of the unit of work. A clean frame, of the one or more clean frames, may be removed from the clean frame queue, responsive to the first request. The clean frame may be delivered to the processor, responsive to the first request.
    Type: Application
    Filed: May 31, 2018
    Publication date: September 27, 2018
    Inventors: Robert Miller, JR., Steven M. Partlow, Thomas F. Rankin, Scott B. Tuttle, Elpida Tzortzatos
  • Patent number: 10061518
    Abstract: In one embodiment, a computer-implemented method includes building an available frame header queue (AFHQ). The AFHQ includes one or more headers, each header including one or more frame references being no more than a maximum count of frame references. Each of the one or more frame references of each of the one or more headers refers to an available frame. A frame request is received for one or more requested frames. One or more frame references are extracted, by a computer processor, from the AFHQ in response to the frame request. The extracting includes extracting from the AFHQ one or more requested headers including the one or more frame references referring to at least a portion of the one or more requested frames.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: August 28, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David Hom, Harris M. Morgenstern, Steven M. Partlow, Scott B. Tuttle, Elpida Tzortzatos
  • Patent number: 10031694
    Abstract: In one embodiment, a computer-implemented method includes producing one or more clean frames by clearing a batch of one or more frames for use in backing virtual memory pages. The producing the one or more clean frames may be performed asynchronously from a unit of work being performed by a processor. The one or more clean frames may be added to a clean frame queue, where the clean frame queue includes a plurality of clean frames that have been cleared. A first request may be received, from the processor, for a frame for use in backing a virtual memory page of the unit of work. A clean frame, of the one or more clean frames, may be removed from the clean frame queue, responsive to the first request. The clean frame may be delivered to the processor, responsive to the first request.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: July 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert Miller, Jr., Steven M. Partlow, Thomas F. Rankin, Scott B. Tuttle, Elpida Tzortzatos
  • Patent number: 9996349
    Abstract: Embodiments of the present invention provide systems and methods for clearing specified blocks of main storage. In one embodiment, an EADM start subchannel is executed. The instructions of the execution of the EADM start subchannel may include a SAP receiving an ADM request block, which specifies a main-storage-clearing operation command. The address and size of a block of main memory to be cleared by the SAP is specified in an MSB designated by the ADM request block.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventors: Anthony F. Coneski, Beth A. Glendening, Dan F. Greiner, Peter G. Sutton, Scott B. Tuttle, Elpida Tzortzatos
  • Publication number: 20180074706
    Abstract: In one embodiment, a computer-implemented method includes building an available frame header queue (AFHQ). The AFHQ includes one or more headers, each header including one or more frame references being no more than a maximum count of frame references. Each of the one or more frame references of each of the one or more headers refers to an available frame. A frame request is received for one or more requested frames. One or more frame references are extracted, by a computer processor, from the AFHQ in response to the frame request. The extracting includes extracting from the AFHQ one or more requested headers including the one or more frame references referring to at least a portion of the one or more requested frames.
    Type: Application
    Filed: November 29, 2017
    Publication date: March 15, 2018
    Inventors: David Hom, Harris M. Morgenstern, Steven M. Partlow, Scott B. Tuttle, Elpida Tzortzatos
  • Patent number: 9898198
    Abstract: In one embodiment, a computer-implemented method includes building an available frame header queue (AFHQ). The AFHQ includes one or more headers, each header including one or more frame references being no more than a maximum count of frame references. Each of the one or more frame references of each of the one or more headers refers to an available frame. A frame request is received for one or more requested frames. One or more frame references are extracted, by a computer processor, from the AFHQ in response to the frame request. The extracting includes extracting from the AFHQ one or more requested headers including the one or more frame references referring to at least a portion of the one or more requested frames.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: February 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David Hom, Harris M. Morgenstern, Steven M. Partlow, Scott B. Tuttle, Elpida Tzortzatos
  • Publication number: 20180032338
    Abstract: Embodiments of the present invention provide systems and methods for clearing specified blocks of main storage. In one embodiment, an EADM start subchannel is executed. The instructions of the execution of the EADM start subchannel may include a SAP receiving an ADM request block, which specifies a main-storage-clearing operation command. The address and size of a block of main memory to be cleared by the SAP is specified in an MSB designated by the ADM request block.
    Type: Application
    Filed: October 23, 2017
    Publication date: February 1, 2018
    Inventors: Anthony F. Coneski, Beth A. Glendening, Dan F. Greiner, Peter G. Sutton, Scott B. Tuttle, Elpida Tzortzatos
  • Publication number: 20180032337
    Abstract: Embodiments of the present invention provide systems and methods for clearing specified blocks of main storage. In one embodiment, an EADM start subchannel is executed. The instructions of the execution of the EADM start subchannel may include a SAP receiving an ADM request block, which specifies a main-storage-clearing operation command. The address and size of a block of main memory to be cleared by the SAP is specified in an MSB designated by the ADM request block.
    Type: Application
    Filed: October 23, 2017
    Publication date: February 1, 2018
    Inventors: Anthony F. Coneski, Beth A. Glendening, Dan F. Greiner, Peter G. Sutton, Scott B. Tuttle, Elpida Tzortzatos
  • Patent number: 9727335
    Abstract: Embodiments of the present invention provide systems and methods for clearing specified blocks of main storage. In one embodiment, an EADM start subchannel is executed. The instructions of the execution of the EADM start subchannel may include a SAP receiving an ADM request block, which specifies a main-storage-clearing operation command. The address and size of a block of main memory to be cleared by the SAP is specified in an MSB designated by the ADM request block.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: August 8, 2017
    Assignee: International Business Machines Incorporated
    Inventors: Anthony F. Coneski, Beth A. Glendening, Dan F. Greiner, Peter G. Sutton, Scott B. Tuttle, Elpida Tzortzatos
  • Patent number: 9715350
    Abstract: In one embodiment, a computer-implemented method includes receiving a large frame area (LFAREA) request, including a request for a plurality of page frame table entries (PFTEs) to back a plurality of frames in an LFAREA of main memory. Each of the plurality of frames has one of a first size and a second size, where the second size is larger than the first size. The method further includes counting how many frames in the main memory have yet to be initialized and have one of the first size and the second size. A size needed for the plurality of PFTEs is calculated, based at least in part on the counting. A storage area is reserved for the plurality of PFTEs, by a computer processor, where a size of the storage area is the size calculated based at least in part on the counting.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: July 25, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Harris M. Morgenstern, Steven M. Partlow, Scott B. Tuttle, Elpida Tzortzatos
  • Patent number: 9715349
    Abstract: Technical solutions for providing real time analytics of a private area of a virtual address space are described. One general aspect includes a method that includes determining, by a processor, a start address and a size of the private area of the virtual address space. The method also includes determining, by the processor, a highest address corresponding to a user region of the private area. The method also includes determining, by the processor, a lowest address corresponding to a high-end region of the private area. The method also includes storing, by the processor, the determined information in a common area outside the virtual address space.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: July 25, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David Hom, Paula M. Spens, Scott B. Tuttle, Elpida Tzortzatos
  • Patent number: 9703501
    Abstract: Technical solutions for providing real time analytics of a private area of a virtual address space are described. One general aspect includes a method that includes determining, by a processor, a start address and a size of the private area of the virtual address space. The method also includes determining, by the processor, a highest address corresponding to a user region of the private area. The method also includes determining, by the processor, a lowest address corresponding to a high-end region of the private area. The method also includes storing, by the processor, the determined information in a common area outside the virtual address space.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: July 11, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David Hom, Paula M. Spens, Scott B. Tuttle, Elpida Tzortzatos
  • Patent number: 9690483
    Abstract: In one embodiment, a computer-implemented method includes producing one or more clean frames by clearing a batch of one or more frames for use in backing virtual memory pages. The producing the one or more clean frames may be performed asynchronously from a unit of work being performed by a processor. The one or more clean frames may be added to a clean frame queue, where the clean frame queue includes a plurality of clean frames that have been cleared. A first request may be received, from the processor, for a frame for use in backing a virtual memory page of the unit of work. A clean frame, of the one or more clean frames, may be removed from the clean frame queue, responsive to the first request. The clean frame may be delivered to the processor, responsive to the first request.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: June 27, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert Miller, Jr., Steven M. Partlow, Thomas F. Rankin, Scott B. Tuttle, Elpida Tzortzatos
  • Patent number: 9658792
    Abstract: In one embodiment, a computer-implemented method includes receiving a large frame area (LFAREA) request, including a request for a plurality of page frame table entries (PFTEs) to back a plurality of frames in an LFAREA of main memory. Each of the plurality of frames has one of a first size and a second size, where the second size is larger than the first size. The method further includes counting how many frames in the main memory have yet to be initialized and have one of the first size and the second size. A size needed for the plurality of PFTEs is calculated, based at least in part on the counting. A storage area is reserved for the plurality of PFTEs, by a computer processor, where a size of the storage area is the size calculated based at least in part on the counting.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: May 23, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Harris M. Morgenstern, Steven M. Partlow, Scott B. Tuttle, Elpida Tzortzatos
  • Publication number: 20170109051
    Abstract: In one embodiment, a computer-implemented method includes producing one or more clean frames by clearing a batch of one or more frames for use in backing virtual memory pages. The producing the one or more clean frames may be performed asynchronously from a unit of work being performed by a processor. The one or more clean frames may be added to a clean frame queue, where the clean frame queue includes a plurality of clean frames that have been cleared. A first request may be received, from the processor, for a frame for use in backing a virtual memory page of the unit of work. A clean frame, of the one or more clean frames, may be removed from the clean frame queue, responsive to the first request. The clean frame may be delivered to the processor, responsive to the first request.
    Type: Application
    Filed: January 5, 2017
    Publication date: April 20, 2017
    Inventors: Robert Miller, JR., Steven M. Partlow, Thomas F. Rankin, Scott B. Tuttle, Elpida Tzortzatos
  • Publication number: 20170090809
    Abstract: Technical solutions for providing real time analytics of a private area of a virtual address space are described. One general aspect includes a method that includes determining, by a processor, a start address and a size of the private area of the virtual address space. The method also includes determining, by the processor, a highest address corresponding to a user region of the private area. The method also includes determining, by the processor, a lowest address corresponding to a high-end region of the private area. The method also includes storing, by the processor, the determined information in a common area outside the virtual address space.
    Type: Application
    Filed: March 14, 2016
    Publication date: March 30, 2017
    Inventors: David Hom, Paula M. Spens, Scott B. Tuttle, Elpida Tzortzatos
  • Publication number: 20170090808
    Abstract: Technical solutions for providing real time analytics of a private area of a virtual address space are described. One general aspect includes a method that includes determining, by a processor, a start address and a size of the private area of the virtual address space. The method also includes determining, by the processor, a highest address corresponding to a user region of the private area. The method also includes determining, by the processor, a lowest address corresponding to a high-end region of the private area. The method also includes storing, by the processor, the determined information in a common area outside the virtual address space.
    Type: Application
    Filed: September 30, 2015
    Publication date: March 30, 2017
    Inventors: David Hom, Paula M. Spens, Scott B. Tuttle, Elpida Tzortzatos