Abstract: An ASIC is disclosed that is formed on a die with multiple functional blocks distributed on the die, each functional block being able to send and to receive data, and each having two inputs labeled slow and fast. The slow input may have a delay component that creates a delay in receiving a data signal, and the fast input may have less delay than the slow input. A switch may be used to couple the slow input and the fast input of a receiving functional block to a data signal based on a distance of the receiving functional block from a sending functional block. The delay in the slow input is used to adjust input data timing to meet setup and hold timing specifications of the functional blocks without altering the ASIC circuit components aside from the functional blocks.

Abstract: An apparatus and method are disclosed for testing a hard macro that is embedded in a system on a chip (SOC) that is included in an integrated circuit chip. The SOC includes the hard macro. A logic design and operation of the hard macro are unknown. A test wrapper is embedded in the SOC. The test wrapper includes a scan chain. The test wrapper surrounds inputs and outputs of the hard macro. The test wrapper receives a known test data pattern in the scan chain that is included in the test wrapper. The hard macro receives from the test wrapper a set of non-test standard SOC inputs when the SOC is not in a test mode and receives the known test data pattern when the SOC is in the test mode. The hard macro generates a set of outputs in response to the inputs. The hard macro is tested utilizing the known test data pattern.