Patents by Inventor Scott C. Best

Scott C. Best has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10387075
    Abstract: A buffer circuit includes a primary interface, a secondary interface, and an encoder/decoder circuit. The primary interface is configured to communicate on an n-bit channel, wherein n parallel bits on the n-bit channel are coded using data bit inversion (DBI). The secondary interface is configured to communicate with a plurality of integrated circuit devices on a plurality of m-bit channels, each m-bit channel transmitting m parallel bits without using DBI. And the encoder/decoder circuit is configured to translate data words between the n-bit channel of the primary interface and the plurality of m-bit channels of the secondary interface.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: August 20, 2019
    Assignee: Rambus Inc.
    Inventor: Scott C. Best
  • Patent number: 10388396
    Abstract: A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: August 20, 2019
    Assignee: Rambus Inc.
    Inventors: Scott C. Best, John Eric Linstadt, Paul William Roukema
  • Patent number: 10360972
    Abstract: A memory system includes dynamic random-access memory (DRAM) component that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. Each DRAM component includes multiplexers that allow either of the data interfaces to write data to or read data from a common set of memory banks, and to selectively relay write and read data to and from other components, bypassing the local banks. Delay elements can impose selected read/write delays to align read and write transactions from and to disparate DRAM components.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: July 23, 2019
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Ely K. Tsern, John Eric Linstadt, Thomas J. Giovannini, Scott C. Best, Kenneth L. Wright
  • Publication number: 20190221249
    Abstract: A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.
    Type: Application
    Filed: December 6, 2018
    Publication date: July 18, 2019
    Inventors: Scott C. Best, Ming Li
  • Publication number: 20190198085
    Abstract: A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 27, 2019
    Inventors: Scott C. Best, Richard E. Warmke, David B. Roberts, Frank Lambrecht
  • Publication number: 20190179690
    Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.
    Type: Application
    Filed: November 7, 2018
    Publication date: June 13, 2019
    Inventors: Thomas J. GIOVANNINI, Catherine CHEN, Scott C. BEST, John Eric LINSTADT, Frederick A. WARE
  • Patent number: 10303623
    Abstract: A first non-volatile memory may store first data and a second non-volatile memory may store second data. An authentication component may be coupled with the first non-volatile memory and the second non-volatile memory and may receive a request to perform an authentication operation. In response to the request to perform the authentication operation, the authentication component may access the first data stored at the first non-volatile memory and the second data stored at the second non-volatile memory and determine whether the second data stored at the second non-volatile memory has become unreliable based on a memory disturbance condition. In response to determining that the second data stored at the second non-volatile memory has become unreliable, a corrective action associated with the first data stored at the first non-volatile memory may be performed.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: May 28, 2019
    Assignee: Cryptography Research, Inc.
    Inventors: Scott C. Best, Brent S. Haukness, Carl W. Werner
  • Publication number: 20190139583
    Abstract: In a data transmission system, one or more signal supply voltages for generating the signaling voltage of a signal to be transmitted are generated in a first circuit and forwarded from the first circuit to a second circuit. The second circuit may use the forwarded signal supply voltages to generate another signal to be transmitted back from the second circuit to the first circuit, thereby obviating the need to generate signal supply voltages separately in the second circuit. The first circuit may also adjust the signal supply voltages based on the signal transmitted back from the second circuit to the first circuit. The data transmission system may employ a single-ended signaling system in which the signaling voltage is referenced to a reference voltage that is a power supply voltage such as ground, shared by the first circuit and the second circuit.
    Type: Application
    Filed: October 1, 2018
    Publication date: May 9, 2019
    Inventors: Scott C. Best, John W. Poulton
  • Publication number: 20190114271
    Abstract: A memory system includes a memory controller coupled to multiple memory devices. Each memory device includes an oscillator that generates an internal reference signal that oscillates at a frequency that is a function of physical device structures within the memory device. The frequencies of the internal reference signals are thus device specific. Each memory device develops a shared reference signal from its internal reference signal and communicates the shared reference signal to the common memory controller. The memory controller uses the shared reference signals to recover device-specific frequency information from each memory device, and then communicates with each memory device at a frequency compatible with the corresponding internal reference signal.
    Type: Application
    Filed: October 18, 2018
    Publication date: April 18, 2019
    Inventors: Scott C. Best, Ian Shaeffer
  • Publication number: 20190073328
    Abstract: This application is directed to a stacked semiconductor device assembly including a plurality of identical stacked integrated circuit (IC) devices. Each IC device further includes a master interface, a channel master circuit, a slave interface, a channel slave circuit, a memory core, and a modal pad configured to receive a selection signal for the IC device to communicate data using one of its channel master circuit or its channel slave circuit. In some implementations, the IC devices include a first IC device and one or more second IC devices. In accordance with the selection signal, the first IC device is configured to communicate read/write data via the channel master circuit of the first IC device, and each of the one or more second IC devices is configured to communicate respective read/write data via the channel slave circuit of the respective second IC device.
    Type: Application
    Filed: October 30, 2018
    Publication date: March 7, 2019
    Inventor: Scott C. Best
  • Publication number: 20190051345
    Abstract: A method of operation in a memory controller is disclosed. The method includes receiving a strobe signal having a first phase relationship with respect to first data propagating on a first data line, and a second phase relationship with respect to second data propagating on a second data line. A first sample signal is generated based on the first phase relationship and a second sample signal is generated based on the second phase relationship. The first data signal is received using a first receiver clocked by the first sample signal. The second data signal is received using a second receiver clocked by the second sample signal.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 14, 2019
    Inventor: Scott C. Best
  • Patent number: 10198314
    Abstract: A memory device is disclosed that includes a row of storage locations to store a data word, and a spare row element. The data word is encoded via an error code for generating error information for correcting X bit errors or detecting Y bit errors, where Y is greater than X. The spare row element has substitute storage locations. The logic is responsive to detected errors to (1) enable correction of a data word based on the error information where there are no more than X bit errors, and (2) substitute the spare row element for a portion of the row where there are at least Y bit errors in the data word.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: February 5, 2019
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Suresh Rajan, Brent Haukness, Scott C. Best, Wayne F. Ellis
  • Patent number: 10192610
    Abstract: A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: January 29, 2019
    Assignee: Rambus Inc.
    Inventors: Scott C. Best, Richard E. Warmke, David B. Roberts, Frank Lambrecht
  • Publication number: 20190012146
    Abstract: The embodiments described herein describe technologies of self-timed pattern generators. The self-timed pattern generators can be used to form a random number generator to generate a random digital value. Asynchronous digital logic in a first generator asynchronously updates a next state based on a current state, a second state of a second generator that is before the first generator in the chain or ring topology, and a third state of a third generator that is after the first generator in the chain or ring topology. The self-timed pattern generators are to output a random digital value based at least in part on the current state output from the first generator.
    Type: Application
    Filed: August 29, 2018
    Publication date: January 10, 2019
    Inventor: Scott C. Best
  • Publication number: 20180364941
    Abstract: A buffer circuit includes a primary interface, a secondary interface, and an encoder/decoder circuit. The primary interface is configured to communicate on an n-bit channel, wherein n parallel bits on the n-bit channel are coded using data bit inversion (DBI). The secondary interface is configured to communicate with a plurality of integrated circuit devices on a plurality of m-bit channels, each m-bit channel transmitting m parallel bits without using DBI. And the encoder/decoder circuit is configured to translate data words between the n-bit channel of the primary interface and the plurality of m-bit channels of the secondary interface.
    Type: Application
    Filed: June 18, 2018
    Publication date: December 20, 2018
    Inventor: Scott C. Best
  • Patent number: 10157660
    Abstract: A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: December 18, 2018
    Assignee: Rambus Inc.
    Inventors: Scott C. Best, Ming Li
  • Patent number: 10146608
    Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: December 4, 2018
    Assignee: Rambus Inc.
    Inventors: Thomas J. Giovannini, Catherine Chen, Scott C. Best, John Eric Linstadt, Frederick A. Ware
  • Patent number: 10133693
    Abstract: A memory system includes a memory controller coupled to multiple memory devices. Each memory device includes an oscillator that generates an internal reference signal that oscillates at a frequency that is a function of physical device structures within the memory device. The frequencies of the internal reference signals are thus device specific. Each memory device develops a shared reference signal from its internal reference signal and communicates the shared reference signal to the common memory controller. The memory controller uses the shared reference signals to recover device-specific frequency information from each memory device, and then communicates with each memory device at a frequency compatible with the corresponding internal reference signal.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: November 20, 2018
    Assignee: Rambus Inc.
    Inventors: Scott C. Best, Ian Shaeffer
  • Publication number: 20180316512
    Abstract: A table key capable of decrypting a first table from a plurality of encrypted tables may be received. Each of the encrypted tables may include at least one pair of values corresponding to a challenge value and a response value. A request to authenticate a secondary device may be received and in response to the request to authenticate the secondary device, a challenge value obtained by using the table key to decrypt an entry in the first table may be transmitted to the secondary device. A second challenge value may be transmitted to the secondary device and a cryptographic proof may be received from the secondary device. The validity of the cryptographic proof received from the secondary device may be authenticated based on the second challenge value and the response value obtained by using the table key to decrypt the entry in the first table.
    Type: Application
    Filed: November 16, 2016
    Publication date: November 1, 2018
    Inventors: Joel Patrick WITTENAUER, Scott C. BEST, Paul Carl KOCHER
  • Patent number: 10114775
    Abstract: This application is directed to a stacked semiconductor device assembly including first and second integrated circuit (IC) devices. Each of the first and second IC devices further includes a master interface, a channel master circuit configured to receive read/write data using the master interface, a slave interface, a channel slave circuit configured to receive read/write data using the slave interface, a memory core coupled to the channel salve circuit, and a modal pad. The first and second IC devices are configured such that in response to at least a modal selection signal received at one of the modal pads of the first and second IC devices, one of the first and second IC devices is configured to receive read/write data using its respective charnel master circuit, and the other of the first and second IC devices is configured to receive read/write data using its respective channel slave circuit.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: October 30, 2018
    Assignee: RAMBUS INC.
    Inventor: Scott C. Best