Abstract: A method for dealing with high inrush current when voltage is applied to mixed voltage logic integrated circuits is disclosed. A depletion N-Channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET) or junction Field Effect Transistor (JFET) is added to a linear voltage regulator in mixed voltage logic integrated circuits. The Field Effect Transistor (FET) is utilized to allow the core voltage to come up with Input/Output voltage prior to turn-on of linear voltage regulator. Turn-on state of FET allows the core voltage to rise with Input/Output voltage until the FET threshold is reached across the gate. When threshold is reached, the FET turns off to allow linear voltage regulator turn on and take over supply power.

Abstract: An amplifier circuit controls the output current through an inductive load. A signal is amplified by one or more op amps, and sourced into a back to back coupling of an NPN transistor and a PNP transistor. In a positive circuit segment, current is sourced to an inductive load, and in a negative segment, current is sunk from the inductive load. The current at the output of the inductive load flows through a resistor, and the resultant voltage drop is negatively fed back to the op amp.

Abstract: A transconductance amplifier generally limits its current output, and specifically decreases its current output as a function of temperature. The circuit is made up of an operational amplifier and two drive transistors that are connected to a first part of the amplifier circuit and a second part of the amplifier circuit respectively. The first part of the circuit is driven by positive input voltages, and the second part of the circuit is driven by negative input voltages. A transistor in each part of the circuit clamps a voltage, thereby limiting the current output. The negative temperature coefficient of the transistor also decreases the output current as the temperature of the circuit rises.

Abstract: A system and method of creating a pulse train signal of a pulse width modulator whose fundamental frequency is time-varying is disclosed. The electrical system includes a pulse width modulator which provides a pulse train signal. The system also includes a power source connected to the pulse width generator. The system further includes a binary counter having an input and a plurality of outputs, wherein the pulse train signal generated by the pulse width modulator is operatively coupled to the input of the binary counter. A plurality of resistors are operatively coupled to the plurality of outputs of the binary counter and operatively coupled to a node. A timing resistor is operatively coupled between a first voltage potential and the node, while a timing capacitor is operatively coupled between the node and a second voltage potential. The node is operatively coupled to an input of the pulse width modulator.

Abstract: An electromagnetic protection ASIC that includes a high transconductance FET switch array operatively arranged to momentarily short all lines of ingress/egress to ground when triggered by a nuclear event detector.

Abstract: An apparatus for controlling voltage sequencing for a power supply having multiple switching regulators includes a first switching regulator, a second switching regulator, a first and second resistors, and a first and second transistors. The first switching regulator provides a positive output voltage at a positive voltage output. The second switching regulator provides a negative output voltage at a negative voltage output. When the voltage at a node between the first and second resistors exceeds a predetermined positive voltage, the first transistor turns on to limit the positive output voltage at the positive voltage output. When the voltage at the node between the first and second resistors drops below a predetermined negative voltage, the second transistor turns on to limit the negative output voltage at the negative voltage output.

Abstract: An apparatus for controlling voltage sequencing for a power supply having multiple switching regulators includes a first switching regulator, a second switching regulator, a first and second resistors, and a first and second transistors. The first switching regulator provides a positive output voltage at a positive voltage output. The second switching regulator provides a negative output voltage at a negative voltage output. When the voltage at a node between the first and second resistors exceeds a predetermined positive voltage, the first transistor turns on to limit the positive output voltage at the positive voltage output. When the voltage at the node between the first and second resistors drops below a predetermined negative voltage, the second transistor turns on to limit the negative output voltage at the negative voltage output.

Abstract: An apparatus for reducing switching regulator noise from outputs of multiple switching regulators is disclosed. The apparatus includes an operational amplifier, an capacitor, a resistor and a pair of diodes. The switching regulators are connected in series to provide a positive output rail and a negative output rail. The output of the operational amplifier in connected to an inverting input of the operational amplifier and a positive sensing input of one of the switching regulators. The non-inverting input of the operation amplifier is connected to the positive output rail of one of the switching regulator via the capacitor. The resistor is connected between a positive voltage output of one of the switching regulators and the capacitors. The pair of diodes is connected between the positive voltage output of one of the switching regulators and the negative output rail of the switching regulators.

Abstract: A transconductance power amplifier for amplifying a signal to a capacitive load, including a first N-channel enhancement MOSFET transistor operatively arranged to source current to the capacitive load, wherein the first N-channel MOSFET transistor has a threshold gate to source voltage, a second N-channel enhancement MOSFET transistor operatively arranged to sink current to the capacitive load, an operational amplifier operatively arranged to transmit and amplify an input signal to both of the first and second MOSFET transistors, and, means for biasing the first N-channel enhancement MOSFET transistor such that its gate to source voltage is always at or above its threshold when the load draws near zero current so that very little additional gate charge is required to turn it on more fully.

Abstract: An electromagnetic protection ASIC that includes a high transconductance FET switch array operatively arranged to momentarily short all lines of ingress/egress to ground when triggered by a nuclear event detector.

Abstract: A bridge amplifier includes a first input node connectable to a power source having an input voltage, a second input node connectable to a control source having a control voltage, and a first and a second output node. A first amplifier module having a gain is coupled between the first and second input nodes and between the first and second output nodes, and a second amplifier module is coupled to the first input node and between the first and second output nodes. The first amplifier module compares a voltage differential between the first and second output nodes to the control voltage and provides an output voltage at the first output node necessary to maintain the voltage differential at a level substantially equal to a product of the control voltage multiplied by the gain.

Abstract: An under voltage lockout {overscore (RESET)} circuit is connected to the {overscore (RESET)} terminal of a EEPROM. The EEPROM is used in a system which may include a computer or processor and which may be used in space. The under voltage lockout {overscore (RESET)} circuit maybe an under voltage lockout circuit used on a LinFinity SG1526/B or a Unitrode UC1526 regulating pulse width modulator which maintain the {overscore (RESET)} voltage low at all values of power supply voltage source voltage less than a predetermined level. In one embodiment the under voltage lockout {overscore (RESET)} circuit output voltage does not have a “floating voltage” which rises to a level higher than its value when a comparator initially senses that a power supply voltage source voltage is less than the predetermined amount. This is a flat {overscore (RESET)} characteristic under voltage lockout.

Abstract: An under voltage lockout {overscore (RESET)} circuit is connected to the {overscore (RESET)} terminal of a EEPROM. The EEPROM is used in a system which may include a computer or processor and which may be used in space. The under voltage lockout {overscore (RESET)} circuit maybe an under voltage lockout circuit used on a LinFinity SG1526/B or a Unitrode UC1526 regulating pulse width modulator which maintain the {overscore (RESET)} voltage low at all values of power supply voltage source voltage less than a predetermined level. In one embodiment the under voltage lockout {overscore (RESET)} circuit output voltage does not have a “floating voltage” which rises to a level higher than its value when a comparator initially senses that a power supply voltage source voltage is less than the predetermined amount. This is a flat {overscore (RESET)} characteristic under voltage lockout.

Abstract: An under voltage lockout {overscore (RESET)} circuit is connected to the {overscore (RESET)} terminal of a EEPROM. The EEPROM is used in a system which may include a computer or processor and which may be used in space. The under voltage lockout {overscore (RESET)} circuit maybe an under voltage lockout circuit used on a LinFinity SG1526/B or a Unitrode UC1526 regulating pulse width modulator which maintain the {overscore (RESET)} voltage low at all values of power supply voltage source voltage less than a predetermined level. In one embodiment the under voltage lockout {overscore (RESET)} circuit output voltage does not have a “floating voltage” which rises to a level higher than its value when a comparator initially senses that a power supply voltage source voltage is less than the predetermined amount. This is a flat {overscore (RESET)} characteristic under voltage lockout.

Abstract: A switching regulator connectable to a DC power supply includes a power switch coupled between a first node and an output node and having a control gate. An output voltage feedback circuit is coupled between the output node and a feedback node. A self-oscillating power switch control circuit is coupled to the first node, the feedback node, and the power switch control gate. The power switch control circuit compares a feedback voltage to a reference voltage and provides a first control voltage to the power switch control gate when the reference voltage exceeds the feedback voltage to turn on the power switch to raise the output voltage, and a second control voltage to the power switch control gate when the feedback voltage exceeds the reference voltage to turn off the power switch to lower the output voltage.

Abstract: A power transistor switched power supply connecting a power source to a capacitive load, including a circuit and method for limiting the inrush surge current through the power transistor. The control gate of a junction field effect transistor (JFET) is coupled between the conductive path of the power transistor and the load to sense voltage drop across the power transistor. The conductive controlled path of the JFET is connected to control the impedance of the power transistor. The JFET shunts some of the power transistor control terminal current during the on transition allowing the power transistor to only turn partially on for a period of time, thus limiting the current through the power transistor from the power source to the load. Because the inrush surge current is limited, the accompanying transient power source voltage drop is reduced with less impact to other circuits connected to the power source.

Abstract: A redundant power supply with a number of loads is coupled to each half of the redundant supply by a respectively different MOSFET switch, with logic gates coupling control signals to the MOSFET switches. The control signal is coupled as one input to the logic gate and the output of the logic gate is connected to the MOSFET switch. The other input of the logic gates for a particular power supply is the output of an overvoltage detection circuit whose output is coupled as an input to all the gates for that power supply. The output of the gates opens the MOSFET switches in response to detection of an overvoltage condition.

Abstract: A power distribution system in which the loads are connected in series to a current source. At each load, a current source to voltage source convertor provides alternative current paths. A serial power distribution current path includes a modulated switch (e.g. a pulse width modulated switch) to control the amount of power delivered to the load via a load current path. The load current path includes a diode which couples a capacitor across the switch, providing a semi-regulated voltage input to a d.c. to d.c. convertor connected across the capacitor. The d.c. to d.c. convertor provides a regulated output voltage, which is connected to the load. The control circuit for modulating the opening and closing of the switch is connected in parallel across the capacitor.

Abstract: A MOSFET switched, redundant power supply has a back-to-back MOSFET switch connecting respectively each power supply to a single load. Each power supply has a positive and negative gate voltage source. In a specific N-channel MOSFET embodiment, the positive (i.e. on) bias is coupled to each switch via a radiation hardened, redundant analogue switch capable of being driven by, for example, a TTL or CMOS microprocessor signal. The negative (i.e. off) bias is coupled to each via a redundant diode pair. In addition, the gates of the back-to-back MOSFET switch for one power source are also connected to the negative bias of the other power source. In this way the MOSFET switch for a failed power supply will be maintained in an off state by the negative bias provided by the redundant supply.

Abstract: A power bus digital communication system reduces power and signal cabling in a space satellite by transformer coupling digital signal sources to power bus circuits, the transformer coupling devices in all power bus circuits being in parallel relation and electrically isolated from a power supply whereby the digital communication sources may communicate among themselves at a DC power level using a square wave modulated according to a Manchester code.