Abstract: Methods and apparatuses are described for an Intellectual Property (IP) Generator for estimating timing, area, and power characteristics of an electronic system design. The IP Generator receives a user-supplied file having data describing a configuration of an IP design having multiple levels of hierarchy. The IP Generator also receives user-supplied technology parameters and data-flow information. The IP generator correlates estimated timing, area, and power characteristics for each IP sub component based on the user supplied technology parameters, data-flow information and configuration parameters. The IP generator reports the timing, area, and power estimates to a user via a graphic user interface prior to a transformation of a Register Transfer Level (RTL) design into the gate-level circuit design.

Abstract: Methods and apparatuses are described for an Intellectual Property (IP) Generator for estimating timing, area, and power characteristics of an electronic system design. The IP Generator receives a user-supplied file having data describing a configuration of an IP design having multiple levels of hierarchy. The IP Generator also receives user-supplied technology parameters and data-flow information. The IP generator correlates estimated timing, area, and power characteristics for each IP sub component based on the user supplied technology parameters, data-flow information and configuration parameters. The IP generator reports the timing, area, and power estimates to a user via a graphic user interface prior to a transformation of a Register Transfer Level (RTL) design into the gate-level circuit design.

Abstract: Methods and apparatuses are described for an Intellectual Property (IP) Generator for estimating timing, area, and power characteristics of an electronic system design. The IP Generator receives a user-supplied file having data describing a configuration of an IP design having multiple levels of hierarchy. The IP Generator also receives user-supplied technology parameters and data-flow information. The IP generator correlates estimated timing, area, and power characteristics for each IP sub component based on the user supplied technology parameters, data-flow information and configuration parameters. The IP generator reports the timing, area, and power estimates to a user via a graphic user interface prior to a transformation of a Register Transfer Level (RTL) design into the gate-level circuit design.

Abstract: The present invention includes a method and apparatus for decomposing and verifying configurable hardware. In one embodiment, the method includes automatically decomposing a set of one or more units at a first level of a configurable hardware system design hierarchy into a set of two or more units of a lower level of the hardware system design hierarchy. The set of one or more units at a first level includes one or more units dynamically instantiated at design creation time as well as at least a first unit composed of a previously instantiated hardware system composed with two or more levels of units within the hardware system design hierarchy of the previously instantiated hardware system.

Abstract: The present invention includes a method and apparatus for decomposing and verifying configurable hardware. In one embodiment, the method includes automatically decomposing a hardware system into a set of one or more units, creating a test-bench for each of the set of units, and verifying each of the set of units before verifying the hardware system design.

Abstract: The present invention includes a method and apparatus for decomposing and verifying configurable hardware. In one embodiment, the method includes automatically decomposing a hardware system into a set of one or more units, creating a testbench for each of the set of units, and verifying each of the set of units before verifying the hardware system design.