Patents by Inventor Scott Choi
Scott Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12224024Abstract: A magnetoresistive random access memory (MRAM) array includes MRAM cells, each MRAM cell having a corresponding Magnetic Tunnel Junction (MTJ) capable of being in a blown state or non-blown state, in which the blown state corresponds to a permanent breakdown of a tunnel dielectric layer of the corresponding MTJ. Write circuitry performs a one-time-programmable (OTP) write operation to blow selected MRAM cells. For each MRAM cell being blown, the write circuitry uses an initial OTP program reference for the MRAM cell being blown to detect onset of tunnel dielectric breakdown after application of each OTP write pulse of the OTP write operation. After detection of the onset, the write circuitry updates the initial OTP program reference, applies at least one additional OTP write pulse to the MRAM cell being blown, and uses the updated OTP program reference to verify that current saturation of the MRAM cell being blown has occurred.Type: GrantFiled: March 23, 2023Date of Patent: February 11, 2025Assignee: NXP USA, Inc.Inventors: Anirban Roy, Nihaar N. Mahatme, Jon Scott Choy
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Publication number: 20240321372Abstract: A magnetoresistive random access memory (MRAM) array includes MRAM cells, each MRAM cell having a corresponding Magnetic Tunnel Junction (MTJ) capable of being in a blown state or non-blown state, in which the blown state corresponds to a permanent breakdown of a tunnel dielectric layer of the corresponding MTJ. Write circuitry performs a one-time-programmable (OTP) write operation to blow selected MRAM cells. For each MRAM cell being blown, the write circuitry uses an initial OTP program reference for the MRAM cell being blown to detect onset of tunnel dielectric breakdown after application of each OTP write pulse of the OTP write operation. After detection of the onset, the write circuitry updates the initial OTP program reference, applies at least one additional OTP write pulse to the MRAM cell being blown, and uses the updated OTP program reference to verify that current saturation of the MRAM cell being blown has occurred.Type: ApplicationFiled: March 23, 2023Publication date: September 26, 2024Inventors: Anirban Roy, Nihaar N. Mahatme, Jon Scott Choy
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Patent number: 12094510Abstract: A magnetoresistive random access memory (MRAM) array includes a data array and a sensor array. Each MRAM cell includes a Magnetic Tunnel Junction (MTJ). Each MRAM cell of the data array stores a data bit. A first and second column of the sensor array are connected to form a sensor column which includes sensor cells, each formed by a first MRAM cell in the first column together with a second MRAM cell in the second column along a same word line. Only one of a first MTJ of the first MRAM cell or second MTJ of the second MRAM cell is used as an MTJ of the sensor cell, and drain electrodes of select transistors of the first and second MRAM cells are electrically connected. Read circuitry provides read data from the data array and a sensor output indicative of a rupture state of an MTJ of the sensor array.Type: GrantFiled: June 17, 2022Date of Patent: September 17, 2024Assignee: NXP USA, Inc.Inventors: Anirban Roy, Thomas Stephen Harp, Nihaar N. Mahatme, Jon Scott Choy
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Patent number: 12051476Abstract: Memory built-in self-test (MBIST) circuitry for a disruptive memory includes an address sequencer configured to select an address with the disruptive memory as a test location, and control circuitry configured to direct a test sequence including a plurality of test operations on the test location. The control circuitry includes a first fault counter and a second fault counter, in which the control circuitry is configured to, after each test operation of the test sequence, determine whether to selectively update a first fault counter and whether to selectively update a second fault counter. The address sequencer, after completion of the test sequence, selects a next address within the disruptive memory as a next test location.Type: GrantFiled: May 11, 2022Date of Patent: July 30, 2024Assignee: NXP USA, Inc.Inventors: Timothy Strauss, Jon Scott Choy, Michael A. Sadd
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Patent number: 11989417Abstract: A main memory includes a first plurality of input/outputs (I/Os) configured to output data stored in the main memory in response to a read access request. A first portion of the first plurality of IOs provides user read data in response to the read access request and a second portion of the first plurality of IOs provides candidate replacement IOs. Repair circuitry is configured to selectively replace one or more IOs of the first portion of IOs using one or more of the candidate replacement IOs of the second portion of IOs to provide repaired read data in response to the read access request in accordance with repair mapping information corresponding to an access address of the read access request. A static random access memory (SRAM) stores repair mapping information, and a repair cache stores cached repair mapping information from the SRAM for address locations of the main memory.Type: GrantFiled: October 31, 2022Date of Patent: May 21, 2024Assignee: NXP USA, Inc.Inventors: Jon Scott Choy, Timothy Strauss, Maurits Mario Nicolaas Storms, Christopher Nelson Hume, Silvia Wagemans
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Publication number: 20240143178Abstract: A main memory includes a first plurality of input/outputs (I/Os) configured to output data stored in the main memory in response to a read access request. A first portion of the first plurality of IOs provides user read data in response to the read access request and a second portion of the first plurality of IOs provides candidate replacement IOs. Repair circuitry is configured to selectively replace one or more IOs of the first portion of IOs using one or more of the candidate replacement IOs of the second portion of IOs to provide repaired read data in response to the read access request in accordance with repair mapping information corresponding to an access address of the read access request. A static random access memory (SRAM) stores repair mapping information, and a repair cache stores cached repair mapping information from the SRAM for address locations of the main memory.Type: ApplicationFiled: October 31, 2022Publication date: May 2, 2024Inventors: Jon Scott Choy, Timothy Strauss, Maurits Mario Nicolaas Storms, Christopher Nelson Hume, Silvia Wagemans
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Publication number: 20230410870Abstract: A magnetoresistive random access memory (MRAM) array includes a data array and a sensor array. Each MRAM cell includes a Magnetic Tunnel Junction (MTJ). Each MRAM cell of the data array stores a data bit. A first and second column of the sensor array are connected to form a sensor column which includes sensor cells, each formed by a first MRAM cell in the first column together with a second MRAM cell in the second column along a same word line. Only one of a first MTJ of the first MRAM cell or second MTJ of the second MRAM cell is used as an MTJ of the sensor cell, and drain electrodes of select transistors of the first and second MRAM cells are electrically connected. Read circuitry provides read data from the data array and a sensor output indicative of a rupture state of an MTJ of the sensor array.Type: ApplicationFiled: June 17, 2022Publication date: December 21, 2023Inventors: Anirban Roy, Thomas Stephen Harp, Nihaar N. Mahatme, Jon Scott Choy
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Publication number: 20230368859Abstract: Memory built-in self-test (MBIST) circuitry for a disruptive memory includes an address sequencer configured to select an address with the disruptive memory as a test location, and control circuitry configured to direct a test sequence including a plurality of test operations on the test location. The control circuitry includes a first fault counter and a second fault counter, in which the control circuitry is configured to, after each test operation of the test sequence, determine whether to selectively update a first fault counter and whether to selectively update a second fault counter. The address sequencer, after completion of the test sequence, selects a next address within the disruptive memory as a next test location.Type: ApplicationFiled: May 11, 2022Publication date: November 16, 2023Inventors: Timothy Strauss, Jon Scott Choy, Michael A. Sadd
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Patent number: 11742012Abstract: A memory includes read circuitry for reading values stored in memory cells. The read circuitry includes flipped voltage followers for providing bias voltages to nodes of current paths coupled to sense amplifiers during memory read operations.Type: GrantFiled: May 28, 2021Date of Patent: August 29, 2023Assignee: NXP USA, INC.Inventors: Karthik Ramanan, Jon Scott Choy, Padmaraj Sanjeevarao
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Patent number: 11521692Abstract: A memory includes a plurality of one-time programmable (OTP) memory cells, wherein each OTP memory cell includes a corresponding storage element capable of being in a permanently blown state or non-blown state. In the non-blown state, the corresponding storage element is capable of being in a low conductive state (LCS) or high conductive state (HCS). Control circuitry is configured to, in response to a received read request having a corresponding access address which selects a set of OTP memory cells, direct write circuitry to apply a voltage differential across the corresponding storage element of each selected OTP memory cell sufficient to set the corresponding storage element to a predetermined one of the LCS or HCS, and, after the write circuitry applies the voltage differential across the corresponding storage element, direct read circuitry to read the selected OTP memory cells to output read data stored in the selected OTP memory cells.Type: GrantFiled: March 18, 2021Date of Patent: December 6, 2022Assignee: NXP USA, Inc.Inventors: Jon Scott Choy, Jacob T. Williams, Karthik Ramanan, Padmaraj Sanjeevarao, Maurits Mario Nicolaas Storms
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Patent number: 11521665Abstract: A non-volatile memory includes resistive cells, write circuitry, and write detect circuitry. Each resistive cell has a resistive storage element and is coupled to a corresponding first column line and corresponding second column line. The write circuitry is configured to provide a write current through a resistive storage element of a selected resistive memory cell during a write operation based on an input data value. The write detect circuitry is configured to generate a reference voltage using a voltage at the corresponding first column line coupled to the selected resistive memory cell at an initial time of the write operation, and, during the write operation, after the initial time, provide a write detect signal based on a comparison between the voltage at the corresponding first column line coupled to the selected resistive memory cell and the reference voltage, wherein the input data value is based on the write detect signal.Type: GrantFiled: May 4, 2021Date of Patent: December 6, 2022Assignee: NXP USA, Inc.Inventors: Jacob T. Williams, Gilles Joseph Maurice Muller, Karthik Ramanan, Jon Scott Choy
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Publication number: 20220383925Abstract: A memory includes read circuitry for reading values stored in memory cells. The read circuitry includes flipped voltage followers for providing bias voltages to nodes of current paths coupled to sense amplifiers during memory read operations.Type: ApplicationFiled: May 28, 2021Publication date: December 1, 2022Inventors: Karthik Ramanan, Jon Scott Choy, Padmaraj Sanjeevarao
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Publication number: 20220358982Abstract: A non-volatile memory includes resistive cells, write circuitry, and write detect circuitry. Each resistive cell has a resistive storage element and is coupled to a corresponding first column line and corresponding second column line. The write circuitry is configured to provide a write current through a resistive storage element of a selected resistive memory cell during a write operation based on an input data value. The write detect circuitry is configured to generate a reference voltage using a voltage at the corresponding first column line coupled to the selected resistive memory cell at an initial time of the write operation, and, during the write operation, after the initial time, provide a write detect signal based on a comparison between the voltage at the corresponding first column line coupled to the selected resistive memory cell and the reference voltage, wherein the input data value is based on the write detect signal.Type: ApplicationFiled: May 4, 2021Publication date: November 10, 2022Inventors: Jacob T. Williams, Gilles Joseph Maurice Muller, Karthik Ramanan, Jon Scott Choy
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Publication number: 20220301647Abstract: A memory includes a plurality of one-time programmable (OTP) memory cells, wherein each OTP memory cell includes a corresponding storage element capable of being in a permanently blown state or non-blown state. In the non-blown state, the corresponding storage element is capable of being in a low conductive state (LCS) or high conductive state (HCS). Control circuitry is configured to, in response to a received read request having a corresponding access address which selects a set of OTP memory cells, direct write circuitry to apply a voltage differential across the corresponding storage element of each selected OTP memory cell sufficient to set the corresponding storage element to a predetermined one of the LCS or HCS, and, after the write circuitry applies the voltage differential across the corresponding storage element, direct read circuity to read the selected OTP memory cells to output read data stored in the selected OTP memory cells.Type: ApplicationFiled: March 18, 2021Publication date: September 22, 2022Inventors: Jon Scott Choy, Jacob T. Williams, Karthik Ramanan, Padmaraj Sanjeevarao, Maurits Mario Nicolaas Storms
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Patent number: 11404118Abstract: A memory includes a pair of sense amplifiers where the pair of sense amplifiers perform a multiphase memory operation to read data from two memory cells. Each sense amplifier includes two current paths. During a first phase of the memory read operation, one of the two sense amplifiers provides current through both a first memory cell and a first reference cell and the other sense amplifier of the two provides current through both a second memory cell and a second reference cell. The reference cells each have different resistance values. During a second phase of the memory read operation, one of the sense amplifiers provides current through both of the first memory cell and the second reference cell and the second sense amplifier provides current through the second memory cell and the first reference cell.Type: GrantFiled: January 27, 2021Date of Patent: August 2, 2022Assignee: NXP USA, INC.Inventors: Michael A. Sadd, Jon Scott Choy
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Publication number: 20220238153Abstract: A memory includes a pair of sense amplifiers where the pair of sense amplifiers perform a multiphase memory operation to read data from two memory cells. Each sense amplifier includes two current paths. During a first phase of the memory read operation, one of the two sense amplifiers provides current through both a first memory cell and a first reference cell and the other sense amplifier of the two provides current through both a second memory cell and a second reference cell. The reference cells each have different resistance values. During a second phase of the memory read operation, one of the sense amplifiers provides current through both of the first memory cell and the second reference cell and the second sense amplifier provides current through the second memory cell and the first reference cell.Type: ApplicationFiled: January 27, 2021Publication date: July 28, 2022Inventors: Michael A. Sadd, Jon Scott Choy
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Patent number: 11348628Abstract: A memory includes virtual ground circuitry configured to generate a virtual ground voltage (greater than zero volts) at a virtual ground node, a memory array of resistive memory cells in which each resistive memory cell includes a select transistor and a resistive storage element and is coupled to a first column line of a plurality of first column lines, and a first decoder configured to select a set of first column lines for a memory read operation from a selected set of the resistive memory cells. The memory includes read circuitry, and a first column line multiplexer configured to couple each selected first column line of the set of first column lines to the read circuitry during the memory read operation, and configured to couple each unselected first column line of the plurality of first column lines to the virtual ground node during the memory read operation.Type: GrantFiled: September 25, 2020Date of Patent: May 31, 2022Assignee: NXP USA, Inc.Inventors: Karthik Ramanan, Jon Scott Choy
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Patent number: 11328784Abstract: A memory includes memory cells having two select transistors per cell. Each of the two select transistors are coupled to two different word lines with each word line being controlled by a separate addressable word line driver circuit. In some embodiments, providing two different word lines from two different word line drivers may provide for a memory where the word lines can apply different voltages based on the memory operation being performed.Type: GrantFiled: September 25, 2020Date of Patent: May 10, 2022Assignee: NXP USA, INC.Inventors: Padmaraj Sanjeevarao, Jon Scott Choy
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Publication number: 20220101902Abstract: A memory includes virtual ground circuitry configured to generate a virtual ground voltage (greater than zero volts) at a virtual ground node, a memory array of resistive memory cells in which each resistive memory cell includes a select transistor and a resistive storage element and is coupled to a first column line of a plurality of first column lines, and a first decoder configured to select a set of first column lines for a memory read operation from a selected set of the resistive memory cells. The memory includes read circuitry, and a first column line multiplexer configured to couple each selected first column line of the set of first column lines to the read circuitry during the memory read operation, and configured to couple each unselected first column line of the plurality of first column lines to the virtual ground node during the memory read operation.Type: ApplicationFiled: September 25, 2020Publication date: March 31, 2022Inventors: Karthik Ramanan, Jon Scott Choy
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Publication number: 20220101934Abstract: A memory includes memory cells having two select transistors per cell. Each of the two select transistors are coupled to two different word lines with each word line being controlled by a separate addressable word line driver circuit. In some embodiments, providing two different word lines from two different word line drivers may provide for a memory where the word lines can apply different voltages based on the memory operation being performed.Type: ApplicationFiled: September 25, 2020Publication date: March 31, 2022Inventors: Padmaraj Sanjeevarao, Jon Scott Choy