Abstract: A memory input signal dynamic logic buffer circuit for providing FET level complementary output signals in response to low level input signals. The circuit is compatible with a variety of bipolar transistor driving logic families as the input signal sensitivity may set external to the circuit. The circuit includes a cross-coupled dynamic latch responsive to gated input and reference signals. Voltage boosting capacitors coupled to the latch nodes provide for simultaneous setting of the latch and boosting of the output nodes, which are connected to dynamic output driver circuits.

Abstract: A differential sense amplifier for semiconductor memory cells is described which uses charge transfer preamplification in combination with a ratioless cross-coupled latch circuit to provide sensing and regeneration of binary information stored in a charge storage device. The sense amplifier may be utilized in arrays of single FET/capacitor memory cells in which the sense amplifier is centrally located and data input/output connections are made at one outside edge of the array. Single bit line driving is made possible by the use of a bit decoder which unconditionally couples charge to a single bit line common mode charge coupling to decrease potentials on a pair of bit lines coupled to the sense amplifier. The common mode bit line discharge means also increases response of the charge transfer preamplifier stage. A single transmission gate device is used for both reading out from a single bit line and writing new data into a memory cell, thus simplifying the input/output circuitry.