Abstract: Technology described herein provides a dynamically reconfigurable processing core. The technology includes a plurality of pipelines comprising a core, where the core is reconfigurable into one of a plurality of core modes, a core network to provide inter-pipeline connections for the pipelines, and logic to receive a morph instruction including a target core mode from an application running on the core, determine a present core state for the core, and morph, based on the present core state, the core to the target core mode. In embodiments, to morph the core, the logic is to select, based on the target core mode, which inter-pipeline connections are active, where each pipeline includes at least one multiplexor via which the inter-pipeline connections are selected to be active. In embodiments, to morph the core, the logic is further to select, based on the target core mode, which memory access paths are active.

Abstract: Embodiments of apparatuses, methods, and systems for scheduling tasks to hardware threads are described. In an embodiment, a processor includes a multiple hardware threads and a task manager. The task manager is to issue a task to a hardware thread. The task manager includes a hardware task queue to store a descriptor for the task. The descriptor is to include a field to store a value to indicate whether the task is a single task, a collection of iterative tasks, and a linked list of tasks.

Abstract: Disclosed embodiments relate to systems and methods for performing instructions to access a compressed graphic list. In one example, a processor includes fetch and decode circuitry to fetch and decode the single instruction to access the compressed graphic list, and execution circuitry to execute the decoded single instruction to cause access to the compressed graphic list by: receiving, from a load store queue, at a first op-engine associated with a first data location, an indirection request, computing, via the first op-engine, a second data location associated with a second op-engine, computing, via the second op-engine, a third data location associated with a third op-engine responsive to the indirection request, and providing, via the third op-engine, a data response to the load store queue responsive to receiving data from the third data location.

Abstract: Embodiments of apparatuses, methods, and systems for a multithreaded processor core with hardware-assisted task scheduling are described. In an embodiment, a processor includes a first hardware thread, a second hardware thread, and a task manager. The task manager is to issue a task to the first hardware thread. The task manager includes a hardware task queue in which to store a plurality of task descriptors. Each of the task descriptors is to represent one of a single task, a collection of iterative tasks, and a linked list of tasks.

Abstract: A fiber optic connector for a plurality of optical fibers includes: a housing portion, a ferrule assembly at least partially disposed in the housing portion, a spring push positioned behind the ferrule, and a spring positioned between the spring push and ferrule. The ferrule assembly includes a ferrule defining an end face of the fiber optic connector and having a plurality of bores arranged in at least two linear rows. The ferrule assembly also includes a ferrule boot coupled to the ferrule, with the ferrule boot including a fiber alignment portion and a cover portion. The fiber alignment portion defines a first groove for a first row of the optical fibers and a second groove for a second row of the optical fibers.

Abstract: A fiber optic connector for a plurality of optical fibers includes: a housing portion, a ferrule assembly at least partially disposed in the housing portion, a spring push positioned behind the ferrule, and a spring positioned between the spring push and ferrule. The ferrule assembly includes a ferrule defining an end face of the fiber optic connector and having a plurality of bores arranged in at least two linear rows. The ferrule assembly also includes a ferrule boot coupled to the ferrule, with the ferrule boot including a fiber alignment portion and a cover portion. The fiber alignment portion defines a first groove for a first row of the optical fibers and a second groove for a second row of the optical fibers.