Abstract: Techniques for broadcast translation lookaside buffer invalidation are described. In some examples, an instance of a single instruction includes fields for a single instruction having fields to indicate one or more operations to perform, an identifier of a first source operand, and, in some examples, an identifier of a second source operand is to be handled by execution circuitry. The execution circuitry of a first hardware thread is to execute the decoded instruction according to the fields to indicate one or more operations to broadcast a command to a plurality of hardware threads to cause an invalidation one or more translation lookaside buffer (TLB) entries for each of the plurality of hardware threads in accordance with a value of the first source operand and/or a value of the second source operand.

Abstract: In embodiments, a memory device includes a memory including at least one memory die layer and a memory controller operatively coupled to the memory. The memory controller is configured to: obtain read/write request for a targeted portion of the memory; obtain data from the targeted portion of the memory in response to the read/write request; and perform a hybrid data correction on the portion of the targeted memory. Performing the hybrid data correction includes performing a Reed Solomon error correction on the data from targeted memory portion; performing Erasure error correction on the data from the targeted memory portion; and correct the targeted memory portion based on outputs of the performed Reed Solomon error correction and the performed Erasure error correction.

Abstract: Techniques for supporting cached and non-cached atomic operations in a scalable shared-memory system are described.

Abstract: Apparatus and method for remote virtual-to-physical address translations.

Abstract: Techniques for offloading function streams are described. In some examples, a function is a sequence of instructions and a stream is a sequence of functions. In some examples, a co-processor is to handle functions and/or function streams provided by a main processor. In some examples, the co-processor includes a plurality of execution resources that at least include one or more of a direct memory access (DMA) engine, an atomic engine, and a collectives engine.

Abstract: Technology described herein provides a dynamically reconfigurable processing core. The technology includes a plurality of pipelines comprising a core, where the core is reconfigurable into one of a plurality of core modes, a core network to provide inter-pipeline connections for the pipelines, and logic to receive a morph instruction including a target core mode from an application running on the core, determine a present core state for the core, and morph, based on the present core state, the core to the target core mode. In embodiments, to morph the core, the logic is to select, based on the target core mode, which inter-pipeline connections are active, where each pipeline includes at least one multiplexor via which the inter-pipeline connections are selected to be active. In embodiments, to morph the core, the logic is further to select, based on the target core mode, which memory access paths are active.

Abstract: Embodiments of apparatuses, methods, and systems for scheduling tasks to hardware threads are described. In an embodiment, a processor includes a multiple hardware threads and a task manager. The task manager is to issue a task to a hardware thread. The task manager includes a hardware task queue to store a descriptor for the task. The descriptor is to include a field to store a value to indicate whether the task is a single task, a collection of iterative tasks, and a linked list of tasks.

Abstract: Disclosed embodiments relate to systems and methods for performing instructions to access a compressed graphic list. In one example, a processor includes fetch and decode circuitry to fetch and decode the single instruction to access the compressed graphic list, and execution circuitry to execute the decoded single instruction to cause access to the compressed graphic list by: receiving, from a load store queue, at a first op-engine associated with a first data location, an indirection request, computing, via the first op-engine, a second data location associated with a second op-engine, computing, via the second op-engine, a third data location associated with a third op-engine responsive to the indirection request, and providing, via the third op-engine, a data response to the load store queue responsive to receiving data from the third data location.

Abstract: Embodiments of apparatuses, methods, and systems for a multithreaded processor core with hardware-assisted task scheduling are described. In an embodiment, a processor includes a first hardware thread, a second hardware thread, and a task manager. The task manager is to issue a task to the first hardware thread. The task manager includes a hardware task queue in which to store a plurality of task descriptors. Each of the task descriptors is to represent one of a single task, a collection of iterative tasks, and a linked list of tasks.