Abstract: Utilities (e.g., systems, methods, etc.) that make use of a secure input/output (I/O) channel between system firmware (e.g., BIOS) and the SP to allow the BIOS to securely send data (e.g., error data) for secure consumption by the SP while preventing or limiting other sources from sending falsified data or the like the SP. The secure I/O channel includes interface hardware (e.g., Field-programmable gate array (FPGA)) that is configured to be unlocked by the BIOS using a security key received from a key generator over a separate security channel. After such data is securely sent to the interface hardware, the BIOS may then pass error interrupt(s) to the OS for performing of any necessary recovery actions. At any appropriate time, the SP may read or consume error data from the memory register of the interface hardware and perform any appropriate diagnoses and/or handling of the error data.

Abstract: Utilities (e.g., systems, methods, etc.) that make use of a secure input/output (I/O) channel between system firmware (e.g., BIOS) and the SP to allow the BIOS to securely send data (e.g., error data) for secure consumption by the SP while preventing or limiting other sources from sending falsified data or the like the SP. The secure I/O channel includes interface hardware (e.g., Field-programmable gate array (FPGA)) that is configured to be unlocked by the BIOS using a security key received from a key generator over a separate security channel. After such data is securely sent to the interface hardware, the BIOS may then pass error interrupt(s) to the OS for performing of any necessary recovery actions. At any appropriate time, the SP may read or consume error data from the memory register of the interface hardware and perform any appropriate diagnoses and/or handling of the error data.

Abstract: Embodiments include systems and methods for in-system, scan-based device testing using novel narrow-parallel (NarPar) implementations. Embodiments include a virtual automated test environment (VATE) system that can be disposed within the operating environment of an integrated circuit for which scan-based testing is desired (e.g., a chip under test, or CuT). For example, the VATE system is coupled with a service processor and with the CuT via a novel NarPar interface. A sequence controller can drive a narrow set of parallel scan pins on the CuT via the NarPar interface of the VATE system in accordance with an adapted test sequence having bit vector stimulants and expected responses. Responses of the CuT to the bit vector stimulants can be read out and compared to the expected results for scan-based testing of the chip.

Abstract: Embodiments include systems and methods for in-system, scan-based device testing using novel narrow-parallel (NarPar) implementations. Embodiments include a virtual automated test environment (VATE) system that can be disposed within the operating environment of an integrated circuit for which scan-based testing is desired (e.g., a chip under test, or CuT). For example, the VATE system is coupled with a service processor and with the CuT via a novel NarPar interface. A sequence controller can drive a narrow set of parallel scan pins on the CuT via the NarPar interface of the VATE system in accordance with an adapted test sequence having bit vector stimulants and expected responses. Responses of the CuT to the bit vector stimulants can be read out and compared to the expected results for scan-based testing of the chip.

Abstract: Embodiments include systems and methods for detecting and/or responding to deficiencies in power interconnect integrity. For example, a first module distributes power to a second module via a high-current mechanical power interconnect. Insufficient integrity in the interconnect can manifest as an impedance, causing potential thermal hazards. A separate (e.g., low-current) interconnect is used to monitor the power being received by the second module from the first module. Embodiments detect when a difference between the power supplied to and received by the second module exceeds a threshold difference, which can indicate deficient interconnect integrity (i.e., a fault). The supply of high-current power to the second module can be substantially immediately interrupted upon detecting the fault.

Abstract: Embodiments include systems and methods for detecting and/or responding to deficiencies in power interconnect integrity. For example, a first module distributes power to a second module via a high-current mechanical power interconnect. Insufficient integrity in the interconnect can manifest as an impedance, causing potential thermal hazards. A separate (e.g., low-current) interconnect is used to monitor the power being received by the second module from the first module. Embodiments detect when a difference between the power supplied to and received by the second module exceeds a threshold difference, which can indicate deficient interconnect integrity (i.e., a fault). The supply of high-current power to the second module can be substantially immediately interrupted upon detecting the fault.