Abstract: The present invention provides unimolecular metal complexes having increased activity in the copolymerization of carbon dioxide and epoxides. Also provided are methods of using such metal complexes in the synthesis of polymers. According to one aspect, the present invention provides metal complexes comprising an activating species with co-catalytic activity tethered to a multidentate ligand that is coordinated to the active metal center of the complex.

Abstract: A catalyst, co-catalyst, and/or chain transfer agent is added at a time after initiation of an addition polymerization reaction to produce a polymer product with a widened molecular weight distribution relative to having all of the components in the original reaction mixture. The catalyst, co-catalyst, or chain transfer agent may be added discretely or continuously to the reaction to produce a product with a bimodal, trimodal, or other broadened molecular weight distribution.

Abstract: A catalyst, co-catalyst, and/or chain transfer agent is added at a time after initiation of an addition polymerization reaction to produce a polymer product with a widened molecular weight distribution relative to having all of the components in the original reaction mixture. The catalyst, co-catalyst, or chain transfer agent may be added discretely or continuously to the reaction to produce a product with a bimodal, trimodal, or other broadened molecular weight distribution.

Abstract: The present invention provides novel polymers and methods of preparing the same.

Abstract: Solutions for solutions for utilizing Inverse Reactive Ion Etching lag in double patterning contact formation are disclosed. In one embodiment, a method includes providing a CMOS device including: an NMOS device having an NMOS gate and a PMOS device having a PMOS gate; a shallow trench isolation located between the NMOS device and the PMOS device; and an inter-level dielectric located over the NMOS device, the PMOS device and the shallow trench isolation; performing a double-patterning etch process on the CMOS device under conditions causing inverse reactive ion etching lag, the performing including forming a first opening, a second opening and a third opening, the second opening being wider than the first opening, and the third opening being contiguous with the second opening; and forming a first contact in the first opening and forming a second contact in both of the second opening and the third opening.

Abstract: A catalyst, co-catalyst, and/or chain transfer agent is added at a time after initiation of an addition polymerization reaction to produce a polymer product with a widened molecular weight distribution relative to having all of the components in the original reaction mixture. The catalyst, co-catalyst, or chain transfer agent may be added discretely or continuously to the reaction to produce a product with a bimodal, trimodal, or other broadened molecular weight distribution.

Abstract: Methods for opening a hard mask and a silicon-on-insulator substrate in a single process chamber are disclosed. In one embodiment, the method includes patterning a photoresist over a stack including an anti-reflective coating (ARC) layer, a silicon dioxide (SiO2) based hard mask layer, a silicon nitride pad layer, a silicon dioxide (SiO2) pad layer and the SOI substrate, wherein the SOI substrate includes a silicon-on-insulator layer and a buried silicon dioxide (SiO2) layer; and in a single process chamber: opening the ARC layer; etching the silicon dioxide (SiO2) based hard mask layer; etching the silicon nitride pad layer; etching the silicon dioxide (SiO2) pad layer; and etching the SOI substrate. Etching all layers in a single chamber reduces the turn-around-time, lowers the process cost, facilitates process control and/or improve a trench profile.

Abstract: Techniques for semiconductor processing are provided. In one aspect, a method for patterning one or more features in a semiconductor device comprises the following step. At least one critical dimension of the one or more features is reduced during etching of the antireflective material. A lithographic structure is also provided.

Abstract: A method for reducing the size of a patterned semiconductor feature includes forming a first layer over a substrate to be patterned, and forming a photoresist layer over the first layer. The photoresist layer is patterned so as to expose portions of the first layer, and the exposed portions of the first layer are removed in a manner so as to create an undercut region beneath the patterned photoresist layer. The patterned photoresist layer is reflowed so as to cause reflowed portions of the patterned photoresist layer to occupy at least a portion of the undercut region.

Abstract: Dual stress liners for CMOS applications are provided. The dual stress liners can be formed from silicon nitride having a first portion for inducing a first stress and a second portion for inducing a second stress. An interface between the first and second stress portions is self-aligned and co-planar. To produce a co-planar self-aligned interface, polishing, for example, mechanical chemical polishing is used.

Abstract: The embodiments of the invention generally relate to an etching process, and more particularly to an etch processing for improving the yield of dielectric contacts on nickel silicides. An oxygen-free feedgas is used in an etching process to reduce or eliminate residuals, including oxidation and consumption of the silicide layer, at the contact surface.

Abstract: (Salph or methoxy salph) Co (initiating ligand) catalyze homopolymerizing rac-PO to produce pure highly isotactic PPO and rac-1-butylene oxide to produce pure isotactic poly(butylene oxide). A product is unfractionated isotactic PPO of m-dyad content >81%, normally at least 99%.

Abstract: An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.

Abstract: An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.

Abstract: Techniques for semiconductor processing are provided. In one aspect, a method for patterning one or more features in a semiconductor device comprises the following step. At least one critical dimension of the one or more features is reduced during etching of the antireflective material. A lithographic structure is also provided.

Abstract: (Salph or methoxy salph) Co (initiating ligand) catalyze homopolymerizing rac-PO to produce pure highly isotactic PPO and rac-1-butylene oxide to produce pure isotactic poly(butylene oxide). A product is unfractionated isotactic PPO of m-dyad content >81%, normally at least 99%.

Abstract: The embodiments of the invention generally relate to an etching process, and more particularly to an etch processing for improving the yield of dielectric contacts on nickel silicides. An oxygen-free feedgas is used in an etching process to reduce or eliminate residuals, including oxidation and consumption of the silicide layer, at the contact surface. The contact resistance at contact surface is reduced, thereby improving the performance of the device.

Abstract: Techniques for semiconductor processing are provided. In one aspect, a method for patterning one or more features in a semiconductor device comprises the following step. At least one critical dimension of the one or more features is reduced during etching of the antireflective material. A lithographic structure is also provided.

Abstract: An apparatus for plasma processing of a wafer includes an annular structure including a magnet, where the structure is concentric with the wafer holder; the magnet generates a magnetic field for deflecting charged particles incident on the structure, thereby preventing damage to the structure by those particles. Accordingly, the structure may be of a material susceptible to erosion during the plasma processing, so that the magnetic field reduces that erosion. The cost of consumable parts in the apparatus is thus reduced. The annular structure may be characterized as a ring having a groove formed therein, with the magnet disposed in the groove. The magnet may be either a permanent magnet or an electromagnet.

Abstract: A method for removing carbon from or stripping a TERA layer. The method includes exposing the TERA layer to a plasma containing an effective amount of nitrogen, and, optionally, oxygen or fluorine. The method is compatible with fluorine based etching systems, and may thus be performed in the same etching system as other etching steps. For example, the method may be performed in the same system as a fluorine based plasma etch for oxide or nitride. The invention includes the method of stripping a TERA layer, etching an oxide layer, and etching a nitride layer in situ in the same etching system. The method is performed at low ion energies to avoid damaging oxide or nitride layers under the TERA film and to provide good selectivity.