Abstract: Programmable data recorders are provided in a network semiconductor chip to monitor and record all or portions of data from various interfaces, including the input and output interfaces of network links interfacing the chip. A data recorder is provided for each network link. The data recorders store captured data in storage arrays. Data may be compressed and associated with time stamps to conserve space in the storage arrays. A data recorder manager in the chip may start and stop the data recorders at approximately the same time. The programmable mode of the data recorders determines which interfaces are monitored, the portion of data captured, and the format of the data in the storage arrays.

Abstract: Programmable data recorders are provided in a network semiconductor chip to monitor and record all or portions of data from various interfaces, including the input and output interfaces of network links interfacing the chip. A data recorder is provided for each network link. The data recorders store captured data in storage arrays. Data may be compressed and associated with time stamps to conserve space in the storage arrays. A data recorder manager in the chip may start and stop the data recorders at approximately the same time. The programmable mode of the data recorders determines which interfaces are monitored, the portion of data captured, and the format of the data in the storage arrays.

Abstract: Programmable data recorders are provided in a network semiconductor chip to monitor and record all or portions of data from various interfaces, including the input and output interfaces of network links interfacing the chip. A data recorder is provided for each network link. The data recorders store captured data in storage arrays. Data may be compressed and associated with time stamps to conserve space in the storage arrays. A data recorder manager in the chip may start and stop the data recorders at approximately the same time. The programmable mode of the data recorders determines which interfaces are monitored, the portion of data captured, and the format of the data in the storage arrays.

Abstract: Programmable data recorders are provided in a network semiconductor chip to monitor and record all or portions of data from various interfaces, including the input and output interfaces of network links interfacing the chip. A data recorder is provided for each network link. The data recorders store captured data in storage arrays. Data may be compressed and associated with time stamps to conserve space in the storage arrays. A data recorder manager in the chip may start and stop the data recorders at approximately the same time. The programmable mode of the data recorders determines which interfaces are monitored, the portion of data captured, and the format of the data in the storage arrays.

Abstract: In a system for operating three address concentrating processors, a common clock signal is transmitted to each of the three address concentrating processors. A common data unit is transmitted simultaneously to each of the three address concentrating processors. A received data unit is received simultaneously from each of the three address concentrating processors. Each of the received data units are compared to each other. An error correcting routine is activated when the data units received from the three address concentrating processors are not all identical.

Abstract: In a first aspect, a first method of injecting one or more errors in data flowing into or out of a chip is provided. The first method includes the steps of (1) generating an error injection pattern indicating one or more bits of data on which a pseudo-random error is to be inserted; and (2) generating an error injection trigger indicating when the pseudo-random error is to be inserted. Numerous other aspects are provided.

Abstract: In a system for operating three address concentrating processors, a common clock signal is transmitted to each of the three address concentrating processors. A common data unit is transmitted simultaneously to each of the three address concentrating processors. A received data unit is received simultaneously from each of the three address concentrating processors. Each of the received data units are compared to each other. An error correcting routine is activated when the data units received from the three address concentrating processors are not all identical.

Abstract: A method, apparatus, system, and signal-bearing medium that in various embodiments determine whether to execute a command in a queue or whether to wait until another command or commands completed. The determination is based on a combination of an in-use vector and a scorecard vector. The in-use vector indicates which slots in various queues contain commands. The scorecard vector indicates the dependencies between various queues. In this way, the scorecard vector, and the thus the queue dependencies can be set and modified after the logic that processes the commands has been designed.

Abstract: A method, apparatus, system, and signal-bearing medium that in various embodiments determine whether to execute a command in a queue or whether to wait until another command or commands completed. The determination is based on a combination of an in-use vector and a scorecard vector. The in-use vector indicates which slots in various queues contain commands. The scorecard vector indicates the dependencies between various queues. In this way, the scorecard vector, and the thus the queue dependencies can be set and modified after the logic that processes the commands has been designed.

Abstract: A method, apparatus, system, and signal-bearing medium that in various embodiments determine whether to execute a command in a queue or whether to wait until another command or commands completed. The determination is based on a combination of an in-use vector and a scorecard vector. The in-use vector indicates which slots in various queues contain commands. The scorecard vector indicates the dependencies between various queues. In this way, the scorecard vector, and the thus the queue dependencies can be set and modified after the logic that processes the commands has been designed.

Abstract: A method and apparatus are provided for implementing input/output IO data management with an I/O buffer (IOB) directory in a compressed memory subsystem. Processor and I/O commands destined for a system memory are identified. I/O cacheline stores are accumulated in a free area of memory until a full block of data is received with only a directory to the data maintained on a memory controller chip. Then a pointer swap is provided to replace the existing compression block.

Abstract: A method and apparatus are provided for implementing locking of non-data page operations in a memory system. In the method for implementing locking of non-data page operations of the invention, checking for a look aside buffer invalidate request is performed. Responsive to identifying a look aside buffer invalidate request, a real address is locked for the look aside buffer invalidate request. Then checking for a non-data page operation is performed. Responsive to identifying a non-data page operation, checking for the non-data page operation to complete is performed. Responsive to identifying the completed non-data page operation, the real address is unlocked for the look aside buffer invalidate request. Only a lock is placed on the page for a non-data page operation. A look aside buffer invalidate sequence is not performed for the non-data page operation.

Abstract: A method and apparatus are provided for implementing input/output IO data management with an I/O buffer (IOB) directory in a compressed memory subsystem. Processor and I/O commands destined for a system memory are identified. I/O cacheline stores are accumulated in a free area of memory until a full block of data is received with only a directory to the data maintained on a memory controller chip. Then a pointer swap is provided to replace the existing compression block.

Abstract: A method and apparatus are provided for implementing locking of non-data page operations in a memory system. In the method for implementing locking of non-data page operations of the invention, checking for a look aside buffer invalidate request is performed. Responsive to identifying a look aside buffer invalidate request, a real address is locked for the look aside buffer invalidate request. Then checking for a non-data page operation is performed. Responsive to identifying a non-data page operation, checking for the non-data page operation to complete is performed. Responsive to identifying the completed non-data page operation, the real address is unlocked for the look aside buffer invalidate request. Only a lock is placed on the page for a non-data page operation. A look aside buffer invalidate sequence is not performed for the non-data page operation.

Abstract: A memory arrangement, where a memory control logic, which drives a memory array, is maintained in a volatile power domain, and clock redrive circuitry, address control redrive circuitry, data transceiver, and the memory array itself are all maintained in a non-volatile power domain, in order to increase the effective life time of a battery backup system. The memory arrangement includes buffering circuitry to prevent leakage currents, and the appropriate control of nets between the memory control logic and the memory array, in order to avoid additional sources of leakage current and bus driver contentions.