Abstract: Systems, methods, and apparatuses for implementing capability-based indirect prefetching are described.

Abstract: Techniques for partitioning and/or gradual re-keying of randomized caches are described. In certain examples, an apparatus includes an execution circuit to cause a memory access request; a cache to store a plurality of sets, each of the sets to include a plurality of cache lines; and a cache randomizer circuit to generate a randomized index into the plurality of sets of the cache based on an address of the memory access request by encrypting a first subset of bits of the address of the memory access request to generate an encrypted value, and generating the randomized index based on a first subset of bits of the encrypted value. The encrypting is to be based on a first key for a first segment of the cache and a second segment of the cache during a first period, on a second key for the first segment of the cache and the first key for the second segment of the cache during a second period, and on the second key for the first segment of the cache and the second segment of the cache during a third period.

Abstract: Techniques for cache scrubbing for cache-set randomization to resist contention-based cache attacks are described. In certain examples, a system includes a memory; an execution circuit to cause a memory access request for the memory; a cache to store a plurality of sets that each include a plurality of cache lines from the memory; a cache randomizer circuit to generate a randomized index into the plurality of sets of the cache based on an address of the memory access request; and a cache scrubber circuit to determine that a number of invalid cache lines in a set of the plurality of sets of the cache is less than a threshold number of invalid cache lines, and in response, invalidate a valid cache line in the set of the plurality of sets of the cache.

Abstract: Techniques for implementing forward-edge control-flow integrity (FECFI) using capability instructions in a hardware processor are described. In certain examples, a hardware processor (e.g.

Abstract: Circuitry and methods for implementing one or more predicated capability instructions are described. In certain examples, a hardware processor (e.g.

Abstract: In one embodiment, an indirect branch is detected in computer program code. The indirect branch calls one of a plurality of functions using a first register. In response, the computer program code is augmented to store an identifier of the indirect branch call in a second register, and the code for each of the plurality of functions is augmented to: determine whether an identifier for the function matches the identifier stored in the second register and render the first register unusable if the identifier for the function does not match the identifier stored in the second register.

Abstract: Systems, methods, and apparatuses for implementing capability-based indirect prefetching are described.

Abstract: Systems, methods, and apparatuses for implementing capability-directed array prefetching are described. In certain examples, a hardware processor comprises an execution circuit to execute an instruction that generates a memory access request for an element in memory; a capability management circuit to check a capability for the memory access request, the capability comprising an address field of the element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of an object to which the capability authorizes access; a cache; and a prefetch circuit to prefetch an additional element of the object from the memory to the cache based on the capability checked by the capability management circuit.

Abstract: Systems, methods, and apparatuses for implementing capability informed prefetches are described.