Abstract: In the present invention, image processing is performed at speeds comparable to those achieved in parallel processing without requiring substantially more area on the substrate than that required in serial processing. In this invention, for an N.times.N processing kernel, N rows of image memory are processed in parallel through a plurality of N floating gate arrays of dimension N.times.N, N-1 of the data rows from the memory being recirculated through the N floating gate structures before being discarded. Each of the floating gate structures is offset from the adjacent floating gate structure by one row so that the data from memory need be recirculated only once.

Abstract: Image processing sections and associated circuitry for generating signals indicative of the centered moments of a sliding submatrix window of signals located within a larger image matrix are disclosed. The processing sections include registers for storing signals indicative of the columnar sums of the signals within an intermediate submatrix of signals and for storing the sum of a subset of the columnar sums that is thereby indicative of the sum of the signals within the sliding submatrix window and, further is equivalent to an uncentered moment of the signals within the sliding submatrix window. The signals stored in the registers are continuously updated as the sliding submatrix window is sequentially moved within the image matrix. The associated circuitry combines the uncentered moment signals to produce centered moment signals.